Memory Systems TRIZ Cases
- Virtual Machine Environment for RTOS on Host OS
A virtual machine environment emulates hardware services and manages interrupts to run real-time operating systems on native host platforms.
- Automatic Type Propagation in Data Flow Programs
A data flow compiler analyzes function outputs to automatically configure implicit downcasting at compile time.
- Virtual Resource Pool Token System for Distributed Storage
A virtual resource pool system uses tokens to represent resource attributes and enforce local allocation policies across distributed storage devices.
- Sub-processor Address Translation for Immediate Data Transfer
A sub-processor executes data transfer using a shared address translation table, eliminating setup delays and stabilizing performance.
- Sparse Matrix Multiplication Memory-Efficient Accumulation Method
Memory-efficient accumulation method for sparse matrix multiplication applications using cache-based processors to allocate buffers for intermediate products.
- Asynchronous Memory Scheduler for Multi-Core Throughput
A scheduler operates at a distinct clock frequency to optimize pending memory access sequences.
- External RAID Controller Merging Drives for Redundancy
An external hardware RAID controller configures a unified storage array using hard disk drives from separate computers.
- Storage Control Device Parallel Formatting Recovery Bitmap
A storage control device manages formatting regions using a bitmap to execute recovery processing in parallel with ongoing volume initialization.
- Physical Register File Bypass via Instruction Tagging
Instruction tagging enables direct result passing between execution units, reducing physical register file size and processing time.
- Automated BAM Dashboard Generation via Template Association
Template-based generation automates Business Activity Monitoring dashboard creation, resolving the conflict between customization needs and development time.
- TLB-Based Cache Bypass for Memory Access Latency
Address translation buffers bypass level one and two caches on misses, reducing data access latency and energy expenditure in computer memory systems.
- Idempotent Transaction Operation Reordering for Failure Recovery
Separates idempotent operations into a distinct sub-sequence to reduce management overhead during failure recovery.
- Storage Profile Abstraction for Virtual Environment Management
Segmented storage policies create abstract profiles that shield virtual environment administrators from system complexity during provisioning.
- Lock-free Bounded FIFO Queue Using Atomic CAS
Atomic compare-and-exchange instructions replace mutex locks in a bounded FIFO queue, eliminating Oracle algorithms and preventing priority inversion.
- Urgency Based Arbiter for Shared Memory Access
An arbiter grants shared memory access using urgency terms derived from buffer depth differences between in-band and out-of-band request identifiers.
- Vector Register Flag Circuitry for Contiguous Gather Memory Access
Flag setting circuitry marks vector registers with contiguous elements to optimize gather memory access operations.
- Hot Deployment of Shared Modules via Delegator Class Loader
Segmenting the single shared class loader into independent module loaders enables hot deployment without system restarts or affecting other applications.
- On-the-Fly Cipher Key Management via Wrap and Protection Keys
Cryptographic engine combines wrap key from internal store with protection key from external memory to generate encryption keys for on-the-fly cipher operations.
- Resource Adapter Suspend Mechanism for Maintenance Quiescing
A resource adapter interface suspends work intake while completing in-flight transactions.
- Dynamic Cache Granularity Partitioning for Mixed CPU-GPU Latency
Segmented cache partitions route requests by size, reducing data access latency and overhead without adding external management logic.
- TLB Probing Prevention via Fault Reporting Delay
Delaying fault reports matches page table walk timing, preventing attackers from probing translation lookaside buffers.
- Asynchronous Memory Scheduler Using Predicted Timing
An asynchronous memory scheduler reorders pending requests using predicted timing and state information to optimize access sequences.