TLB-Based Cache Bypass for Memory Access Latency
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Solution Overview
Problem
In computer memory systems, cache misses lead to increased latency and energy expenditure due to the need to check if requested data is in the cache, even though it is not available.
Innovation Solution
The proposed solution involves performing address translation using a translation lookaside buffer (TLB) and taking actions such as bypassing level 1 (L1) and level 2 (L2) caches, or speculatively sending memory requests to the L2 cache, in response to a TLB miss to reduce data access latencies and energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the cache is checked for every memory request, then the cache hit rate is improved, but the data access latency increases when a TLB miss occurs
Solution Approach 1:
The system dynamically adjusts cache access behavior based on TLB status. When a TLB miss occurs, the cache access is bypassed; when a TLB hit occurs, normal cache access proceeds. This dynamic adaptation resolves the contradiction by optimizing the cache access path according to real-time translation buffer status.
Solution Approach 2:
The invention changes the access parameter (cache bypass vs. normal access) based on the TLB miss/hit status. By modifying the access behavior parameter dynamically, the system achieves both goals: maintaining cache hit rate for successful translations while minimizing latency for translation misses.
2Reliability
If the cache is checked for every memory request, then the cache functionality is fully utilized, but the energy expenditure increases due to unnecessary checks during TLB misses
Solution Approach 1:
The system dynamically controls cache access based on TLB status to optimize energy consumption. When a TLB miss is detected, the system dynamically disables cache access for that request, avoiding unnecessary energy expenditure while maintaining full cache functionality for valid translations.
Solution Approach 2:
The invention extracts the cache access operation from the mandatory path and makes it conditional. By removing the cache check from the execution path during TLB misses, the system eliminates unnecessary energy consumption while preserving cache functionality when needed.
3Productivity
If cache access is performed for all requests, then resource utilization is maximized, but the processing speed decreases due to sequential checking
Solution Approach 1:
The system performs preliminary checking of TLB status before proceeding to cache access. This preliminary action allows the system to skip cache access entirely when a TLB miss is detected, thereby increasing processing speed without permanently reducing resource utilization, as cache access is restored for subsequent valid requests.
Solution Approach 2:
The invention implements a skipping mechanism where the cache access step is bypassed (skipped) when a TLB miss occurs. This rushing through of the cache check stage for invalid translations significantly increases processing speed while maintaining full resource utilization for valid cacheable requests.
Data Source
AI summary
Address translation is performed to translate a virtual address targeted by a memory request (e.g., a load or memory request for data or an instruction) to a physical address. This translation is performed using an address translation buffer, e.g., a translation lookaside buffer (TLB). One or more actions are taken to reduce data access latencies for memory requests in the event of a TLB miss where the virtual address to physical address translation is not in the TLB. Examples of actions that are performed in various implementations in response to a TLB miss include bypassing level 1 (L1) and level 2 (L2) caches in the memory system, and speculatively sending the memory request to the L2 cache while checking whether the memory request is satisfied by the L1 cache.