Asynchronous Data Pipeline with Alternating Mousetrap Stages
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Solution Overview
Problem
Asynchronous data pipelines face latency and throughput issues due to long feedback loops and the need for additional control handling when stages are placed closer together, leading to increased power consumption and timing delays compared to synchronous pipelines.
Innovation Solution
Incorporating multiple mousetrap elements with request and data latches in each pipeline stage, controlled by a phase signal that alternates between configurations, allowing data transmission before acknowledgment receipt, and using fork and join control circuits to share wires, thereby reducing latency and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If asynchronous pipelines use per-stage feedback to transmit data, then data transmission can occur without global clock, but feedback loop delay doubles the latency compared to synchronous pipelines
Solution Approach 1:
The patent segments the feedback loop into two independent paths: a request path for sending data forward and an acknowledgment path for receiving confirmation. By allowing the request path to proceed without waiting for acknowledgment, the effective latency is reduced while maintaining asynchronous operation benefits.
Solution Approach 2:
The patent implements preliminary action by allowing data to be transmitted on the request path before the acknowledgment feedback is received. This enables overlapping of transmission and acknowledgment receipt, effectively halving the latency compared to sequential operation while maintaining data integrity through the acknowledgment mechanism.
2Loss of time
If pipeline stages are placed closer together to reduce latency, then transmission distance decreases, but additional control handling increases power consumption and complexity
Solution Approach 1:
The patent segments control functions into dedicated fork control circuits and join control circuits. These specialized circuits handle the control overhead efficiently, allowing stages to be placed closer together without proportionally increasing power consumption from control logic.
Solution Approach 2:
Instead of having each stage wait for acknowledgment before proceeding (traditional asynchronous approach), the patent inverts the approach by allowing continuous forward progression on the request path and handling acknowledgments separately. This reduces the control overhead per stage while maintaining data integrity.
3Speed
If synchronous pipelines include retiming stages with registers for all signals, then data can traverse distances within clock cycles, but hardware overhead increases with approximately 2N flip-flop elements per stage
Solution Approach 1:
The patent extracts the clock signal forwarding requirement from the data transmission path. By using asynchronous handshaking with request and acknowledgment signals instead of synchronous clocked registers, the design eliminates the need for 2N flip-flop elements per retiming stage while maintaining data transmission integrity across clock domain boundaries.
Solution Approach 2:
The patent introduces request and acknowledgment signals as intermediaries between pipeline stages. These mediator signals enable data transmission without requiring complex retiming logic or large numbers of flip-flops, reducing hardware overhead while maintaining synchronization between stages.
4Reliability
If asynchronous pipelines wait for acknowledgment feedback before transmitting next data element, then data integrity is maintained, but throughput is reduced to half of synchronous pipelines
Solution Approach 1:
The patent segments the data transmission flow into independent request paths and acknowledgment paths. Multiple request paths can operate simultaneously, allowing multiple data elements to be in transit at the same time, thereby increasing throughput while maintaining data integrity through the acknowledgment mechanism.
Solution Approach 2:
The patent enables continuity of useful action by allowing the request path to continuously transmit data without interruption for acknowledgment receipt. The acknowledgment mechanism operates in parallel, ensuring data integrity without blocking the continuous forward progression of data elements, thus maintaining high throughput.
Data Source
AI summary
One embodiment of the present invention sets forth a data pipeline, which includes a first mousetrap element and a second mousetrap element in a first pipeline stage. Each mousetrap element includes a request latch that, when enabled, allows a request signal to pass from the first pipeline stage to a second pipeline stage following the first pipeline stage in the data pipeline. Each mousetrap element also includes a data latch that, when enabled, allows a data element to pass from the first pipeline stage to the second pipeline stage. Each mousetrap element further includes a latch controller that enables and disables the request and data latches based on a phase signal that alternates between a first value that configures the first mousetrap element to transmit data to the second pipeline stage and a second value that configures the second mousetrap element to transmit data to the second pipeline stage.