Logic Circuits Characterised By Logic Function TRIZ Cases
- Look-Ahead Clock Gating for Event-Driven TOF Sensor Pipelines
Early SPAD event detection releases downstream clocks only when needed, cutting TOF sensor pipeline power without delaying response.
- Battery Contactor Protection Circuit for Fusion Bonding Faults
A hardwired SR latch and AND gate open the negative contactor when positive contact fusion is detected, preventing repeated bonding faults.
- CMOS Nanosheet Layout With Asymmetric Active Region Widths
Asymmetric active region widths in CMOS nanosheet transistors balance driving current and capacitance while preserving fine-pitch integration.
- Spacecraft Latch Current Limiter Using Resistive Overcurrent Mode
An LLC-controlled latch current limiter shifts a spacecraft switch into resistive mode to curb overcurrent before cutoff and allow fault recovery.
- Standardized FPGA Logic Drive With NVM for Low-NRE Custom Logic
Using standardized FPGA and NVM chips on an interposer, this case cuts ASIC NRE and manufacturing complexity while keeping logic field-programmable.
- FDSOI Well Structure for Mixed Threshold Back-Biasing
A buried Nwell and shared well regions enable mixed-threshold FDSOI transistors with flexible back biasing while reducing chip area.
- FPGA and NVM Interposer Logic Drive for Low-NRE Scaling
Standardized FPGA chips paired with NVM on an interposer cut ASIC-level NRE costs while keeping field programmability at advanced nodes.
- Backside-Routed IC Gate Layout for Reduced Cell Pitch
Back-side metallization adds routing paths between stacked gates, cutting front-side congestion to reduce IC pitch and standard cell area.
- MOSFET Interlock Circuit for Energy Storage Short-Circuit Prevention
Cross-coupled feedback and interlock circuits block simultaneous MOSFET turn-on, preventing battery short-circuits in energy storage systems.
- Stacked Planar Capacitive Threshold Gate for Low-Transistor Logic
Reset-phase threshold tuning lets stacked planar capacitors implement multiple logic functions with fewer transistors and lower power.
- Oscillation Monitoring Circuit for Fast Semiconductor Defect Detection
An integrated oscillation-and-counting circuit detects semiconductor defects early, improving inspection accuracy without slowing production.
- Burst Mode PWM Control With Sleep Suppression at Nominal Load
Feedback-driven burst logic suppresses sleep periods at nominal load to preserve voltage regulation while keeping light-load converter efficiency.
- Spin Logic Gates Using Electrochemical Potential Reconfiguration
Gate-voltage-controlled ferromagnetic channels reconfigure spin logic functions beyond silicon scaling limits while avoiding added magnetic-field changes.
- Charge Pump Gate Timing to Suppress Breakthrough Current
Non-overlapping transistor gate timing in a charge pump suppresses breakthrough current, preserving boosted voltage while cutting power consumption.
- Oscillation Monitoring Circuit for Threshold Voltage Defect Detection
By counting oscillation rises or falls tied to threshold voltage, this circuit detects semiconductor defects faster and more accurately during processing.
- Crash Switch Circuit for Noise-Tolerant Signal Hold
A diode-capacitor crash switch holds a reference voltage long enough to transmit reliable crash signals despite power issues and ripple noise.
- Backside Power Rail Layout for ECO-Driven IR Drop Reduction
Varying-width backside power rails cut IR drop and voltage droop during semiconductor ECOs without changing the frontside cell layout.
- FinFET Multiplexer Layout With Lower Transistor Count
A FinFET multiplexer removes transmission gates to cut transistor count, shrink area usage, and improve speed and power efficiency.