Charge Pump Gate Timing to Suppress Breakthrough Current
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Solution Overview
Problem
Existing charge pump circuits in motor drive systems face challenges in efficiently boosting voltage while minimizing breakthrough currents, which can reduce the output voltage and increase power consumption.
Innovation Solution
The charge pump circuit incorporates a configuration of capacitors, transistors, and gate control circuits that manage the switching states of transistors Tr1 and Tr2, and transistors Tr3 and Tr4, to prevent breakthrough currents by controlling the voltage levels and transitions during clock signal changes, thereby optimizing voltage boosting and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stress or pressure
If a charge pump circuit is used to generate voltage higher than power supply voltage, then the output voltage is improved, but breakthrough currents occur that reduce efficiency and increase power consumption
Solution Approach 1:
The patent implements dynamic control of transistor switching timing based on clock signal phases. The first transistor switches at the rising edge of the clock signal while the second transistor switches at the falling edge, creating non-overlapping conduction periods. This dynamic temporal separation prevents breakthrough currents while maintaining efficient voltage boosting operation.
Solution Approach 2:
The gate control circuit prepares transistor switching states in advance by generating gate signals that anticipate voltage transitions. The circuit ensures that transistors are switched to appropriate states before breakthrough conditions can develop, preventing energy loss before it occurs.
2Power
If voltage boosting is performed in a motor drive system, then the power supply capability is improved, but breakthrough currents reduce the efficiency of the charge pump circuit
Solution Approach 1:
The charge pump circuit is segmented into two independent pumping units, each with dedicated transistors and control signals. The first pumping unit uses transistor Tr1 controlled by a first clock signal, while the second pumping unit uses transistor Tr2 controlled by a second clock signal. This segmentation allows independent optimization of each unit and prevents mutual interference that causes breakthrough currents.
Solution Approach 2:
The circuit employs periodic switching of transistors synchronized to clock signal phases. Transistor Tr1 switches periodically at the rising edge of the clock signal, while transistor Tr2 switches periodically at the falling edge. This periodic non-overlapping operation maintains continuous voltage boosting while eliminating breakthrough currents that would reduce efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses breakthrough currents, maintains high output voltage, and minimizes power consumption, allowing for a more compact and efficient charge pump circuit implementation in drive devices.
Implementation Method 1
a first capacitor C1 including a first end to which a first voltage is supplied; a second capacitor C2 including a first end to which a first pulse signal is supplied
Implementation Method 2
a first transistor Tr1 including a first end coupled to a second end of the first capacitor C1, and a second end coupled to a first node N1; a second transistor Tr2 including a first end coupled to the first end of the first capacitor C1, and a second end coupled to the first node N1
Data Source
AI summary
A charge pump circuit includes a first capacitor including a first end supplied for a voltage, and a second end; a second capacitor including a third end supplied for a pulse signal, and a fourth end coupled to a node; a third capacitor including a fifth end supplied for the pulse signal, and sixth end; a first transistor including a seventh end coupled to the second end, an eighth end coupled to the node, and a first gate; a second transistor including a ninth end coupled to the first end, a tenth end coupled to the node, and a second gate; and a circuit including a first terminal coupled to the node, a second terminal coupled to the sixth end, a third terminal coupled to the first gate, and a fourth terminal coupled to the second gate.