FDSOI Well Structure for Mixed Threshold Back-Biasing
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Solution Overview
Problem
Current fully depleted semiconductor-on-insulator chip structures face challenges with increased chip area consumption due to physical separation of well areas and limited design flexibility resulting from restricted back biasing options.
Innovation Solution
An area-efficient fully depleted semiconductor-on-insulator structure with mixed threshold voltage transistors and both forward and reverse back biasing options, featuring a buried Nwell, multiple well regions, and transistors on an insulator layer, allowing for electrical connections to receive bias voltages that maintain reverse biasing of PN junctions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If physical separation between regular well and flip well areas is implemented, then PN junction forward biasing is avoided, but chip area consumption increases
Solution Approach 1:
The patent merges the regular well area and flip well area into a single integrated well structure, eliminating the need for physical separation. This is achieved by configuring transistors within the same well region and using selective gate control to prevent PN junction forward biasing, thereby reducing chip area while maintaining reliability
Solution Approach 2:
The patent transitions from a lateral separation approach (spatial dimension) to a vertical/control-based approach (control dimension). By using multi-gate transistor configurations and selective biasing control, the patent achieves PN junction protection without requiring lateral physical separation between well areas
2Reliability
If all transistors are configured as LVT or SLVT FETs in flip well area, then forward back biasing is achieved, but design flexibility is limited
Solution Approach 1:
The patent applies different threshold voltage characteristics to different transistors within the same well area. By enabling mixed LVT and HVT transistor configurations, each transistor can be optimized for its specific function while maintaining forward back biasing control through selective gate configurations
Solution Approach 2:
The patent introduces dynamic biasing control through multi-gate transistor configurations, allowing the biasing state to be adjusted based on operational requirements. This enables transistors to switch between different operating modes (forward back biasing, reverse back biasing, or no back biasing) depending on the specific circuit needs
3Reliability
If all transistors are configured as RVT or HVT FETs in regular well area, then reverse back biasing is achieved, but design flexibility is limited
Solution Approach 1:
The patent enables different threshold voltage characteristics (LVT and HVT) to coexist within the same regular well area by using selective transistor configurations. This allows individual transistors to be optimized for specific functions while maintaining reverse back biasing control through appropriate gate configurations
Solution Approach 2:
The patent creates a universal well structure that can accommodate multiple transistor types (LVT and HVT) and support multiple biasing modes (forward back biasing, reverse back biasing, or no back biasing). This multi-functional well configuration eliminates the need for separate dedicated well areas for different transistor types
Data Source
AI summary
Disclosed is a fully depleted semiconductor-on-insulator structure including a buried Nwell in a substrate below P-type and N-type well regions, an insulator layer on the substrate, and mixed threshold voltage transistors on the insulator layer above at least one of the well regions. An Nwell can be connected to receive a positive bias voltage with any NFET and any PFET above being a FBB LVT/SLVT NFET and a RBB RVT/HVT PFET, respectively. A Pwell can be connected to receive another positive bias voltage less than the positive bias voltage on the Nwell with any NFET and any PFET above being a FBB RVT/HVT NFET and a RBB LVT/SLVT PFET, respectively. Additionally, or alternatively, a Pwell can be connected to receive a negative bias voltage with any NFET and any PFET above being a RBB RVT/HVT NFET and a FBB LVT/SLVT PFET, respectively.