CMOS Nanosheet Layout With Asymmetric Active Region Widths
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Solution Overview
Problem
The increasing demand for high-performance, high-speed, and multifunctional semiconductor devices requires finer patterns with narrower widths and smaller separation distances, while also overcoming the limitations of planar metal oxide semiconductor field effect transistors (FETs) by developing FinFETs with three-dimensional channel structures.
Innovation Solution
A semiconductor device is designed with multiple active regions on a substrate, each with channel layers spaced apart perpendicularly to the substrate surface, and gate structures crossing these regions to optimize electrical characteristics. The device includes a CMOS structure with N-type and P-type transistors, where the widths of the active regions are adjusted to balance driving current and capacitance, thereby improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the width of active regions is reduced to increase integration density, then the degree of integration is improved, but the driving current decreases
Solution Approach 1:
The patent applies different width ratios to different active regions based on their conductivity type. P-type active regions have a wider width relative to N-type active regions, compensating for the lower hole mobility in P-type transistors. This local differentiation ensures that each transistor type contributes equally to the driving current despite the overall reduction in active region widths for high integration density.
Solution Approach 2:
The patent changes the width parameter of active regions based on conductivity type. By setting the width ratio between P-type and N-type active regions to be greater than 1:1 (specifically 1.1:1 to 1.5:1), the patent adjusts the electrical parameters to balance the driving currents of complementary transistors while maintaining fine pitch for high integration.
2Productivity
If the separation distance between patterns is reduced to increase integration, then the degree of integration is improved, but the manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The patent introduces asymmetric width relationships between P-type and N-type active regions. By making P-type active regions wider than N-type active regions, the design creates an asymmetric layout that can be more tolerant to manufacturing variations while maintaining the fine pitch required for high integration degree.
3Reliability
If the active region width is made asymmetric between P-type and N-type transistors to balance current, then the electrical characteristics are improved, but the device complexity increases
Solution Approach 1:
The patent implements local quality by differentiating the width of active regions based on conductivity type. P-type active regions are designed with greater width than N-type active regions to compensate for lower hole mobility. This localized differentiation improves electrical characteristics by balancing driving currents while maintaining a relatively simple overall device structure.
Data Source
AI summary
A semiconductor device includes a substrate including a first device region and a second device region, active regions spaced apart from each other on the substrate, having a constant width, extending in a first direction parallel to an upper surface of the substrate and including a first active region and a second active region provided on the first device region and a third active region and a fourth active region provided on the second device region, a plurality of channel layers provided on the active regions and configured to be spaced apart from each other in a direction perpendicular to the upper surface of the substrate, gate structures provided on the substrate and extending to cross the active regions and the plurality of channel layers, and source/drain regions provided on the active regions on at least one side of the gate structures.