Backside Power Rail Layout for ECO-Driven IR Drop Reduction
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Solution Overview
Problem
The frequent need for engineering change orders (ECOs) in semiconductor device design and manufacturing to address performance degradation or improve integration density and performance leads to significant time and resource costs due to the requirement for substantial redesign of cell architectures, especially when existing power grids cause excessive current-resistance drops and dynamic voltage droops.
Innovation Solution
Incorporating a backside power distribution network (BSPDN) with varying width backside power rails disposed below the cells, allowing for flexible power rail arrangements not bound by frontside design rules, which reduces the need for substantial redesign by addressing IR drops and dynamic voltage droops without altering the existing circuit layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing power grids are used in frontside cell architecture, then initial design is simpler, but excessive current-resistance drops and dynamic voltage droops occur causing performance degradation
Solution Approach 1:
The patent introduces a backside power distribution network (BSPDN) that delivers power from the backside of the semiconductor device to the cells, adding a spatial dimension to the power distribution architecture. This allows power rails to be positioned closer to the cells without occupying frontside interconnect space, thereby reducing current-resistance drops and dynamic voltage droops while maintaining frontside design simplicity.
2Reliability
If engineering change orders are issued to modify cell architecture for performance improvement, then device performance can be enhanced, but significant time and resource costs are incurred due to substantial redesign requirements
Solution Approach 1:
The patent segments the power distribution function into a separate backside network, independent from the frontside cell logic and interconnect architecture. This segmentation allows the power delivery mechanism to be modified or optimized without requiring changes to the cell logic design, enabling performance improvements while minimizing redesign time and costs.
Solution Approach 2:
By moving power distribution to the backside dimension, the patent enables independent optimization of power delivery without affecting frontside cell architecture. This dimensional separation allows ECOs to address power-related performance issues without triggering substantial redesign of the cell logic, thereby reducing time and resource costs.
3Ease of manufacture
If uniform width power rails are used in backside architecture, then manufacturing is simpler, but connection flexibility is limited when addressing different cell power requirements
Solution Approach 1:
The patent implements power rails with varying widths at different locations on the backside, where each width is optimized for the specific power requirements of the cells it serves. This local quality variation allows the backside power network to adapt to different cell power demands while maintaining a relatively simple overall architecture that does not require complete redesign for different configurations.
Data Source
AI summary
A semiconductor device includes: a plurality of cells including 1st cells arranged in a 1st row of a layout of the semiconductor device; and a 1st backside power rail and a 2nd backside power rail disposed below the 1st cells, extended in a 1st direction, and arranged in a 2nd direction intersecting the 1st direction, wherein the 1st backside power has a 1st width, and the 2nd backside power rail has a 2nd width which is different from the 1st width.