FinFET Multiplexer Layout With Lower Transistor Count
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Solution Overview
Problem
Existing digital multiplexer (DMUX) circuits face challenges in reducing area-cost and improving performance, with traditional designs often requiring high transistor counts and consuming more power while compromising on speed.
Innovation Solution
The implementation of DMUX circuits using FinFET architecture and innovative logic circuits without transmission gates, which reduce transistor counts and optimize layout structures to minimize area usage and enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If traditional DMUX circuits are used, then the circuit can perform multiplexing function, but the area utilization is large and transistor count is high
Solution Approach 1:
The DMUX circuit is divided into separate functional blocks: input circuitry with individual transistors for each data input, select circuitry with transistors controlled by select signals, and output circuitry with transmission gates. This segmentation allows optimized transistor placement and reduced overall transistor count while maintaining full multiplexing functionality.
Solution Approach 2:
The patent employs transmission gates that operate in two dimensions (controlled by both select signal and its complement), allowing more efficient signal routing and reducing the number of transistors needed compared to traditional single-dimension control schemes. This dimensional approach enables compact layout and reduced area utilization.
2Speed
If traditional DMUX circuits are used, then the circuit can perform multiplexing function, but the power consumption is high and speed is compromised
Solution Approach 1:
The output circuitry uses transmission gates that can dynamically switch between conducting and blocking states based on select signals. This dynamic operation allows the circuit to activate only the necessary signal paths, reducing power consumption while maintaining high speed operation when switching between different data inputs.
Solution Approach 2:
The patent extracts and eliminates unnecessary transistor components from traditional DMUX designs. By using a optimized configuration with individual transistors for inputs and selective transmission gates for outputs, the design removes redundant transistors that would otherwise consume power and slow down signal propagation.
Data Source
AI summary
A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.