Backside-Routed IC Gate Layout for Reduced Cell Pitch
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) become smaller and more complex, the resistance of conductive lines within these digital devices changes, affecting operating voltages and overall IC performance.
Innovation Solution
The integration circuit includes a first gate on a first level and a second gate on a second level, with the second level below the first level, and these gates are coupled together. Additionally, a first input pin is electrically coupled to the third gate from the back-side of the substrate, utilizing back-side metallization levels as additional routing resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional routing methods are used, then IC performance is maintained, but pitch and area increase
Solution Approach 1:
The patent utilizes the back-side of the substrate as an additional dimension for routing signals. By implementing metallization levels on the back-side and routing signals through this dimension, the patent reduces the routing complexity and area requirements on the front-side, directly resolving the technical contradiction between area reduction and routing complexity.
2Productivity
If back-side metallization is utilized, then routing efficiency improves, but manufacturing complexity increases
Solution Approach 1:
The patent divides the IC into front-side and back-side components, with each side having its own metallization levels and routing paths. This segmentation allows independent optimization of each side's manufacturing process, reducing the overall manufacturing complexity while improving routing efficiency through the additional back-side dimension.
Data Source
AI summary
A integrated circuit includes a first, a second, a third, and a fourth gate, a first input pin and a first conductor. The first and third gate are on a first level. The second and fourth gate are on a second level. The second gate is coupled to the first gate. The fourth gate is coupled to the third gate. The first input pin extends in a second direction, is on a first metal layer above a front-side of a substrate, is coupled to the first gate, and configured to receive a first input signal. The first input pin is electrically coupled to the third gate by the first, second or fourth gate. The first conductor extends in the first direction, is on a second metal layer below a back-side of the substrate, and is coupled to the second and fourth gate.