Asynchronous Pipeline Scan Chains for Clockless Circuit Testing
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Solution Overview
Problem
Traditional scan-based testing methods are ineffective for asynchronous pipelines, requiring significant additional circuitry that increases power consumption and area, making it difficult to test and debug these circuits without modifying them.
Innovation Solution
A method and apparatus for testing asynchronous pipelines, which includes forming data and control scan chains using scannable latch circuits, allowing for independent testing of control and data portions by scanning test data and control data into the pipeline, latching, capturing results, and scanning them out for analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional scan-based testing methods are applied to asynchronous pipelines, then testing capability is achieved, but significant additional circuitry (extra latches and multiplexers) is required, increasing power consumption and circuit area
Solution Approach 1:
The existing latches in the asynchronous pipeline are designed to serve dual purposes: their primary function of data storage during normal operation and their secondary function as scan chain elements during testing. By making the latches universal (capable of both data latching and scan operations), the patent eliminates the need for separate scan chain latches, thereby reducing circuit area while maintaining full testing capability.
Solution Approach 2:
The latches in the asynchronous pipeline are designed to be self-sufficient by incorporating scan capability directly into their structure. Each latch can independently operate in either data mode or scan mode based on control signals, eliminating the need for external scan chain infrastructure and reducing overall circuit complexity.
2Reliability
If traditional scan-based testing methods are applied to asynchronous pipelines, then testing capability is achieved, but power consumption increases due to additional circuitry
Solution Approach 1:
The latches are designed to perform both data storage and scan operations, eliminating the need for separate scan chain latches that would consume additional power. By reusing existing latches for dual purposes, the patent reduces overall power consumption while maintaining complete testing functionality.
Solution Approach 2:
The latches independently handle both data operation and scan operations without requiring additional dedicated scan circuitry. This self-sufficient design eliminates the power overhead associated with separate scan chain infrastructure.
3Reliability
If traditional scan-based testing methods are applied to asynchronous pipelines, then testing can be performed, but the lack of reference clock compatibility creates testing limitations
Solution Approach 1:
The patent introduces local control signals (scan enable, data enable, clear) that can be applied individually to each latch or group of latches without requiring a global reference clock. This localized control approach allows testing to proceed in an asynchronous manner compatible with clockless circuit operation, while still providing the structured control needed for systematic testing.
Solution Approach 2:
The patent changes the control parameters from clock-edge-triggered synchronization to asynchronous control signals. By using level-sensitive or event-driven control mechanisms instead of edge-triggered clock synchronization, the scan testing methodology is adapted to work naturally with asynchronous pipelines that lack a reference clock signal.
Data Source
AI summary
A method and apparatus for test of asynchronous pipelines. An asynchronous data pipeline includes first and second pluralities of pipeline stages in an alternating sequence. Each of the pipeline stages includes a control circuit, a latch circuit configured to latch data responsive to an indication from the control circuit, and a combinational logic circuit coupled to receive data from an output of the latch circuit. Each of the latch circuits is scannable. The latch circuits of the first and second pluralities of pipeline stages form a data scan chain configured to load test data into the combinational logic circuits during testing of the data pipeline. The data pipeline further includes a control scan chain configured to load control data for operating the control circuits during testing of the data pipeline. Testing of the data pipeline can include independent testing of the control portion or the data portion.