Asynchronous SRAM Circuit Using C-Elements for SEE Fault Tolerance

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Solution Overview

Problem

Asynchronous electronic circuits are vulnerable to transient faults, particularly single-event effects (SEEs) and single-event upsets (SEUs), which can cause functionality issues and deadlocks due to the absence of a clock signal for filtering glitches, and existing fault-tolerant solutions are not applicable to asynchronous circuits.

Innovation Solution

The development of a fault-tolerant SRAM circuit design that replicates signals and uses C-elements and staticizer circuits to prevent single-event effects from changing the overall state of the circuit during transient faults, employing series transistors and cross-coupled C-elements to ensure independent operation of replica nodes and correct error propagation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If asynchronous circuits are used to eliminate clock signal and reduce power consumption, then energy efficiency is improved, but the circuits become vulnerable to transient faults and single-event effects

Engineering Contradiction:
Improvepower consumptionVSAvoidimmunity to transient faults
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The circuit is divided into multiple independent signal paths (original path and inverted path) that process the same information independently. Each path is evaluated separately by C-elements, allowing the system to segment the computation and compare results to detect faults without requiring a clock signal.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent creates redundant copies of the circuit logic by generating inverted signals through separate paths. These copied paths process the same input data independently, and their outputs are compared using C-elements to detect single-event upsets. This copying approach enables fault detection in asynchronous circuits without increasing power consumption significantly.

Inventive Principle:
Principle #26Copying

2Reliability

If radiation hardening techniques are applied to protect against single-event effects, then reliability is improved, but device complexity and manufacturing difficulty increase

Engineering Contradiction:
Improveimmunity to single-event effectsVSAvoidcircuit structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Instead of using complex radiation hardening techniques, the patent employs a simpler approach by creating redundant inverted signal paths and using C-elements for comparison. This copying method achieves single-event effect immunity with minimal additional circuit complexity, avoiding the need for specialized manufacturing processes.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The circuit performs self-diagnosis by comparing results from independent inverted paths. The C-elements automatically detect discrepancies caused by single-event upsets without external intervention, enabling the circuit to self-correct or self-flag errors without complex external monitoring systems.

Inventive Principle:
Principle #25Self-service

3Reliability

If redundant signal paths are added to detect single-event upsets, then fault detection capability is improved, but circuit area and power consumption increase

Engineering Contradiction:
Improvefault detection capabilityVSAvoidcircuit area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges the fault detection function with the existing computation logic by using the same inverted signal paths for both data processing and fault detection. The C-elements serve dual purposes: they evaluate the inverted paths for computation and simultaneously compare results for fault detection, eliminating the need for separate detection circuitry and reducing overall circuit area.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS8004877B2Fault tolerant asynchronous circuits
Publication Date: 2011.08.23 ACHRONIX SEMICONDUCTOR CORP
  • US8004877B2 patent drawing
  • US8004877B2 patent drawing
  • US8004877B2 patent drawing

AI summary

New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, for example of the type introduced through radiation or, more broadly, single-event effects. SEE-tolerant configurations are shown and described for combinational logic circuits, state-holding logic circuits and SRAM memory circuits.