ATE Interface Segmentation for High-Speed DUT Testing
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Solution Overview
Problem
The challenge in testing digital semiconductor devices is the limited memory available on-chip during production testing, which restricts the size and complexity of test programs, and the need for high-speed memory interfaces that are not easily accessible during wafer probe testing.
Innovation Solution
The solution involves using a two-step interface approach in automatic test equipment (ATE), where a first interface, typically a slow debug interface, is used to upload a program to the device under test (DUT) that configures it to open a second, high-speed interface, allowing for faster communication and memory extension.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a slow debug interface is used to upload test programs to the DUT, then the interface is accessible during wafer probe testing, but the data transfer rate is low and testing time is extended
Solution Approach 1:
The patent segments the interface usage into two phases: initial program upload via the slow debug interface, followed by high-speed data transfer via the activated high-speed interface. This segmentation allows each interface to be used for its optimal purpose while resolving the contradiction between accessibility and speed.
Solution Approach 2:
The patent performs preliminary action by using the slow debug interface to upload and execute a program that activates the high-speed interface before actual high-speed testing begins. This preliminary setup enables subsequent high-speed operations while maintaining initial accessibility.
2Ease of operation
If on-chip memory resources are used for test programs, then the memory is accessible during wafer level testing, but the memory size is limited restricting test program complexity
Solution Approach 1:
The patent transitions from on-chip memory (one dimension) to off-chip memory (another dimension) by activating the high-speed interface that connects to external memory resources. This dimensional change allows access to significantly larger memory capacities while maintaining accessibility through the activated interface.
Solution Approach 2:
The patent introduces the high-speed interface as an intermediary between the DUT and off-chip memory resources. This intermediary enables communication with external memory that would otherwise be inaccessible during wafer probe testing, effectively extending the available memory capacity.
3Productivity
If high-speed memory interfaces are used for testing, then the data transfer rate is high, but the interfaces are not accessible during wafer probe test insertion
Solution Approach 1:
The patent performs preliminary activation of the high-speed interface through program execution via the debug interface before utilizing the high-speed interface for data transfer. This preliminary action makes the previously inaccessible high-speed interface available during the testing process.
Solution Approach 2:
The patent implements self-service by having the DUT automatically activate its own high-speed interface through executed program code, eliminating the need for external physical connection changes or manual interface switching during wafer probe testing.
4Quantity of substance
If test program code is separated into smaller pieces to fit limited memory, then the test can be executed with available resources, but the testing process becomes more complex and time-consuming
Solution Approach 1:
The patent moves test program storage from the constrained on-chip memory dimension to the expansive off-chip memory dimension accessible via the high-speed interface. This allows the entire test program to be stored as a single unit rather than fragmented pieces, reducing complexity while providing adequate storage capacity.
Data Source
AI summary
The automated test equipment is configured to establish communication, e.g. by uploading a program to the DUT using a first interface, such as a debug interface or a generic interface having access to the processing unit for external control. A typical use case of the first interface is debug access to the DUT, which typically requires limited data rates. In the case of the invention the first interface is an ATE access for test execution. The first interface configures the DUT to open a second interface running at much higher data rate, which is higher than the first interface, for additional communication. Additionally, the second interface may have extended capabilities compared to the first interface, such as presenting its own memory to the processing unit of the DUT as a normal system memory.