Memory Queue Operations to Increase Throughput in ATE Systems
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Solution Overview
Problem
Conventional Automated Test Equipment (ATE) systems struggle to keep up with the increasing data rates and complex protocols of emerging devices, such as high-performance SSDs, due to the limitations of Field-Programmable Gate Arrays (FPGAs) in implementing main bus protocols like PCIe Generation 5 and PCIe CXL.
Innovation Solution
The implementation of a memory block queue mechanism that uses a CPU to generate test patterns and buffer write data, allowing for simultaneous generation and application of test patterns, thereby enabling high-speed pattern generation and overcoming the limitations of conventional DMA techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FPGAs are used to implement main bus protocols like PCIe Generation 5 and PCIe CXL, then design flexibility and time to market are improved, but the data generation and transfer rates become insufficient for high-performance devices
Solution Approach 1:
The system divides the test pattern generation function into two separate components: a CPU that generates test patterns at high speed using software algorithms, and an FPGA that handles protocol conversion and interface control. This segmentation allows each component to optimize for its specific function, with the CPU providing high-speed data generation and the FPGA providing protocol adaptability.
Solution Approach 2:
The patent introduces a buffer memory as an intermediary between the CPU and the FPGA/test interface. The CPU writes test patterns to the buffer at high speed, and the FPGA reads from the buffer and converts the data to the required protocol format. This intermediary buffer decouples the speed requirements from the protocol conversion requirements, allowing both to operate at their optimal speeds.
2Device complexity
If conventional DMA techniques are used for data transfer, then hardware-based pattern generation is simplified, but the throughput cannot keep up with increasing data rates of emerging devices
Solution Approach 1:
The patent replaces the conventional hardware-based pattern generation mechanism (using FPGA logic and DMA) with a software-based approach using a CPU. The CPU executes software algorithms to generate test patterns, which are then transferred to the buffer. This substitution leverages the superior computational speed and flexibility of modern CPUs while maintaining the simplicity of hardware-based transfer through the buffer interface.
3Speed
If hardware-based APG is used to generate test patterns, then maximum data generation speed is achieved, but the system cannot adapt to main bus protocols like PCIe
Solution Approach 1:
The CPU serves as a universal pattern generator that can implement multiple test algorithms and adapt to different protocol requirements through software. Instead of requiring separate hardware implementations for each protocol, the CPU can load different software routines to generate patterns for PCIe, CXL, or other interfaces, providing universal adaptability while maintaining high-speed generation capabilities.
Data Source
AI summary
A tester system includes a test computer system for coordinating and controlling testing of a plurality of devices under test (DUTs), and a hardware interface board coupled to the test computer system and controlled by the test computer system. The hardware interface board is operable to apply test input signals to the plurality of DUTs and operable to receive test output signals from the plurality of DUTs, the hardware interface board including: a processor operable to access test pattern data for application to a DUT. The tester system also includes a memory coupled to the processor and including a plurality of buffers, the plurality of buffers organized into a first-in-first-out (FIFO) memory queue including a buffer front end and a buffer back end, the plurality of buffers operable to receive the test pattern data from the processor at the buffer front end, a direct memory access (DMA) engine coupled to the memory and operable for reading data out of the buffer back end and supplying test pattern data to the DUT, a buffer table for maintaining a buffer sequence within the plurality of buffers and for maintaining vacancy and occupancy information regarding the plurality of buffers, and driver hardware coupled to the DMA engine and operable to receive the test pattern data and for driving the test input signals to the plurality of DUTs.