ATE Test Pattern Generation Using HVL DUT Models
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Solution Overview
Problem
Existing methods for generating test patterns for integrated circuits are lengthy and inefficient, particularly when simulating millions or billions of devices, due to the complexity of structural models.
Innovation Solution
Utilizing a Hardware Verification Language (HVL) model to simulate the input-output behavior of integrated circuits obliviously to their internal circuitry, followed by a simulation and translation process to generate test patterns, significantly reducing simulation time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If structural models are used to simulate integrated circuits, then simulation accuracy is maintained, but simulation time becomes excessively long
Solution Approach 1:
The patent creates a simplified copy of the integrated circuit model in HVL that captures only the essential input-output behavior without replicating the complex internal circuitry. This abstract model serves as a functional copy that is much faster to simulate while maintaining accuracy for test pattern generation purposes.
Solution Approach 2:
The patent extracts only the necessary input-output relationship from the complex structural model, separating the essential functional behavior from the unnecessary internal detail. By taking out only the critical input-output mapping, the model achieves both speed and accuracy for testing purposes.
2Productivity
If detailed structural models are used, then test pattern accuracy is improved, but test pattern generation efficiency deteriorates
Solution Approach 1:
The patent changes the modeling parameters from detailed structural representations to high-level abstract representations. By changing the level of abstraction in the model parameters, the system achieves both fast simulation and accurate test pattern generation without needing to simulate every internal circuit detail.
Data Source
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AI summary
An apparatus for generating Automatic Test Equipment (ATE) testing patterns to test an electronic device-under-test (DUT) that includes electrical circuitry, at least one input port and at least one output port. The apparatus includes a memory and a processor. The memory is configured to store (i) a hardware verification language (HVL) model of the IC, including a model input that models the at least one DUT input port and a model output that models the at least one OUT output port, the HVL model configured to determine, obliviously to the electrical circuitry, a logic state of the model output responsively to a logic state of the model input, and (ii) a simulation program, configured to simulate the HVL model of the DUT. The processor is configured to generate an ATE testing pattern for the DUT by running the simulation program.