Atomic Counter Update Module for SoC Coherence
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Solution Overview
Problem
Existing computing systems face inefficiencies in updating counters, particularly due to the need for multiple commands and the use of spin locks or semaphores, which consume processing power and disrupt system coherence when updating counters across shared cache and memory locations.
Innovation Solution
A system-on-chip (SoC) with a counter update module that atomically updates counters based on commands from processing cores, generating error correction codes (ECC) and writing the updated values, with separate modules handling cached and non-cached counter updates, ensuring operations are transparent to the processing cores and preventing interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple commands and spin locks are used to update counters, then counter updates can be performed, but processing power is consumed and system coherence is disrupted
Solution Approach 1:
The patent extracts the counter update functionality from the processing cores and places it in dedicated counter update modules. This separation allows the processing cores to issue simple commands without being involved in the complex update logic, spin locks, or coherence management, thereby reducing processing power consumption and maintaining system coherence while ensuring reliable counter updates.
2Reliability
If spin locks or semaphores are used for counter updates, then update integrity is maintained, but processing overhead increases
Solution Approach 1:
The patent removes spin locks and semaphores from the counter update process by extracting update functionality to dedicated modules. These modules perform atomic updates directly without requiring processing cores to wait for locks or manage synchronization, eliminating the processing overhead associated with these mechanisms while preserving update integrity through hardware-level atomic operations.
Solution Approach 2:
The patent replaces the software-based synchronization mechanism (spin locks/semaphores) with a hardware-level atomic update mechanism. The dedicated counter update modules perform atomic operations directly in hardware, eliminating the need for software-based locking and reducing processing overhead while maintaining update integrity.
3Productivity
If counters are updated through multiple commands, then updates can be performed, but system coherence is disrupted
Solution Approach 1:
The patent extracts counter update operations from the general processing core workflow and handles them in dedicated counter update modules. This extraction allows processing cores to issue simple atomic update commands without disrupting system coherence, as the specialized modules manage the update process independently without requiring complex coordination or locking mechanisms.
Data Source
AI summary
Some of the embodiments of the present disclosure provide a system-on-chip (SOC) that includes a plurality of processing cores; and a counter update module configured to atomically update a counter that is stored in a storage location, based on a counter update command received from a processing core of the plurality of processing cores; generate an ECC for the updated value of the counter; and write the updated value of the counter and the ECC to the storage location. Other embodiments are also described and claimed.