Atomic GPU Burst Execution to Reduce SRAM Access
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Solution Overview
Problem
GPU register files, implemented in SRAMs, consume significant power and area due to the large capacity required for parallel threads, and frequent accesses lead to increased power consumption and bank clashes.
Innovation Solution
A separate sub-processor within the GPU executes bursts of instructions atomically, using flip-flop based registers and a dedicated instruction cache to reduce SRAM accesses, thereby minimizing power consumption and area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a large capacity of register files is used to support a large number of parallel threads, then the GPU can execute more parallel threads, but the power consumption and area increase significantly
Solution Approach 1:
The register file is segmented into multiple banks, allowing parallel access to different portions of the register file simultaneously. This reduces the time required to access register data and decreases the overall power consumption by enabling concurrent operations across multiple thread blocks.
Solution Approach 2:
The patent introduces a hierarchical register file structure with multiple levels of caching. Frequently accessed register data is cached in faster, smaller register files closer to the execution units, while less frequently accessed data is stored in larger, slower register files. This dimensional organization reduces the average access time and power consumption.
2Adaptability or versatility
If a large capacity of register files is used to support a large number of parallel threads, then the GPU can execute more parallel threads, but the area occupied by register files increases
Solution Approach 1:
The register file is divided into multiple smaller banks that can be accessed in parallel. This segmentation allows the same functional capacity to be achieved with a more compact physical layout, reducing the overall area occupied while maintaining support for a large number of parallel threads.
Solution Approach 2:
The register file banks are designed to be universally accessible by multiple execution units and thread blocks. Each bank can serve multiple purposes and be shared across different functional units, reducing the total amount of dedicated register storage needed and thereby reducing the overall area required.
3Productivity
If frequent accesses are made to register files, then thread execution can proceed efficiently, but power consumption increases due to frequent SRAM accesses
Solution Approach 1:
The patent implements a register prefetch mechanism that anticipates future register access needs and loads required data into the register file banks in advance. This preliminary action reduces the frequency of actual register accesses during thread execution, thereby reducing power consumption while maintaining execution efficiency.
Solution Approach 2:
The register file design ensures continuous availability of required data through multiple parallel access ports and banks. This allows thread execution to proceed without stalling for register accesses, maintaining high productivity while the parallel architecture distributes the power consumption across multiple independent banks.
4Productivity
If frequent accesses are made to register files, then thread execution can proceed efficiently, but bank clashes occur which reduce performance
Solution Approach 1:
The register file is divided into multiple independently accessible banks, allowing simultaneous access from multiple execution units without conflicts. This segmentation eliminates bank clashes by providing dedicated access paths for each bank, ensuring consistent performance even under high thread execution loads.
Solution Approach 2:
The patent introduces a multi-dimensional addressing scheme for the register file that allows different thread blocks to access different banks simultaneously. This dimensional organization of access paths eliminates conflicts by distributing access requests across multiple dimensions of the register file structure, maintaining both efficiency and reliability.
Data Source
AI summary
A graphics processing unit has a shader core including a main processing portion and a sub-processor. The main processing portion comprises a scheduler, an instruction cache, a plurality of registers and a plurality of arithmetic logic units (ALUs). The sub-processor operates independently of the main processing portion and comprises a burst scheduler, a plurality of registers and a plurality of ALUs. The sub-processor is arranged to execute bursts, wherein a burst comprises at least one group of instructions that can be executed atomically and which are extracted from a program. The main processing portion executes a modified version of the program, wherein the modified program is created from the program by replacing the instructions in a burst with an instruction that triggers the execution of the burst. The registers in the sub-processor are used to store one or more sources and/or results for bursts that are being executed by the sub-processor.