Atomic Layer Etch for High-k Dielectric Thickness Control
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Solution Overview
Problem
The miniaturization of semiconductor devices poses challenges in controlling the thickness of high-k gate dielectric layers and metal gate conductors, as conventional etching techniques struggle to achieve precise control, leading to issues like polysilicon gate depletion, high gate resistance, and leakage current, especially in CMOS technology where different dielectric materials are required for NMOS and PMOS devices.
Innovation Solution
An atomic layer etch (ALE) process is employed to precisely remove thin layers of material by altering the crystalline structure of the surface layer and using selective etchants like HF or HCl, allowing for the controlled removal of monolayers or sub-monolayers of transition metal oxides and high-k dielectric materials, enabling the formation of multi-level dielectric structures with precise thickness control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching techniques are used on high-k dielectric materials, then the etching process is simpler and faster, but the thickness control precision deteriorates
Solution Approach 1:
The etching process is divided into multiple sequential steps (modification step followed by etching step) rather than a single conventional etching step. This segmentation allows precise control of thickness by controlling the number of cycles and parameters of each step, achieving atomic-level precision while managing complexity through systematic process design
Solution Approach 2:
The surface layer of the high-k dielectric material is modified before etching to make it more susceptible to selective removal. This preliminary modification action enables precise thickness control by creating a distinct chemical or structural state at the surface that can be selectively etched with controlled depth, solving the precision-control problem without requiring overly complex etching conditions
2Reliability
If dielectric layer thickness is reduced to optimize device performance, then transistor performance improves, but leakage current increases due to substrate damage
Solution Approach 1:
The conventional mechanical/chemical etching process is replaced with a modified sequential process involving surface modification followed by controlled etching. This substitution reduces substrate damage by using gentler, more selective removal mechanisms that don't require aggressive chemistry or high energy, thereby reducing leakage current while maintaining thin layer precision
Solution Approach 2:
The etching parameters (chemistry, temperature, time, power) are precisely controlled and optimized to achieve selective removal of the modified surface layer without damaging the underlying substrate. By changing and controlling these parameters, the process achieves atomic-level thickness control while minimizing substrate damage that would cause leakage current
3Reliability
If different dielectric materials are used for NMOS and PMOS devices, then device optimization improves, but process complexity increases
Solution Approach 1:
The patent applies different dielectric materials to different device regions (NMOS vs PMOS) by using the selective etching process to remove material from specific areas. The modified surface layer can be selectively etched in certain regions while leaving other regions intact, allowing local optimization of device performance with different materials without requiring completely separate fabrication lines
Solution Approach 2:
The sequential modification-etching process serves multiple functions: it provides precise thickness control, enables selective area etching, and supports different dielectric materials. This multi-functional process reduces overall process complexity by consolidating what would otherwise require separate specialized processes for each device type
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for precise and controlled removal of extremely thin layers, addressing the challenges of high-k material etching and enabling the optimization of transistor performance by allowing for atomic-level thickness control of dielectric layers, reducing leakage currents and improving device parameters.
Implementation Method 1
modifying an exposed thin surface layer of the dielectric layer by applying energized ions
Implementation Method 2
removing the exposed thin surface layer from the dielectric layer with an etchant
Data Source
AI summary
A semiconductor process and apparatus includes forming first and second gate electrodes (151, 161) by forming the first gate electrode (151) over a first high-k gate dielectric (121) and forming the second gate electrode (161) over at least a second high-k gate dielectric (122) different from the first gate dielectric (121). Either or both of the high-k gate dielectric layers (121, 122) may be formed by depositing and selectively etching an initial layer of high-k dielectric material (e.g., 14). As deposited, the initial layer (14) has an exposed surface (18) and an initial predetermined crystalline structure. An exposed thin surface layer (20) of the initial layer (14) is prepared for etching by modifying the initial crystalline structure in the exposed thin surface layer. The modified crystalline structure in the exposed thin surface layer may be removed by applying a selective etch, such as HF or HCl.