Decorative Surface Effects TRIZ Cases

A solder mask coats the MEMS pressure port interior to block molten solder during reflow attachment.

A method for producing thin MEMS chips on an SOI substrate using a sacrificial oxide layer and back-side etching.

Grounded membranes shield IC pressure sensor electrodes from external fields, resolving accuracy degradation during high-density integration.

Chemical etching and oxidation modify copper surfaces to achieve high joint strength with PBT or PPS resins, preventing gas leakage in electronic components.

A microplasma jet generator uses a flat meandering micro-antenna driven by VHF power to create inductively coupled plasma.

Uniform access holes in the MEMS cap ensure predictable undercut progression, preventing contaminant exposure during sacrificial layer removal.

Replacing standard dielectrics with a thin high dielectric constant layer reduces surface resistance and extends operating life by lowering applied voltage.

Moisture-resistant passivation layers shield exposed glass areas and bonding interfaces in MEMS sensors from environmental humidity.

A porous polycrystalline silicon membrane integrates with a semiconductor cap to enable aeriform fluidic communication through controlled selective porosity.

Segmented electrodes on a dummy membrane enable differential capacitance measurement that cancels thermo-mechanical stress drift.

Ultra-low stabilizer levels prevent hydrolysis degradation while intercepting UV radiation to retain tensile strength.

Removing the bottom electrode eliminates complex wafer alignment and anode bonding, enabling efficient resonant torsional motion for bidirectional sensing.

Depositing a sealing layer over a vent hole hermetically seals the MEMS cavity, reducing package height and stress-induced deflections.

A plug seals a through-hole in a MEMS cap layer, enabling independent gas atmospheres across separate cavities on one die.

Multi-layer mask stacks and spin-on-carbon barriers enable sub-40nm patterns, resolving overlay alignment issues in double patterning.

Vertical integration separates CMOS and MEMS devices across the substrate thickness, reducing cross-talk without adding shielding complexity or chip space.

A MEMS micro-mirror sandwich structure reduces mass while maintaining stiffness.

Varying temperature and pressure conditions breaks strong gallium nitride binding structures to enable efficient semiconductor layer removal.

Guard rings isolate metallic bonding pads in MEMS packages, preventing lateral spreading that causes electrical shorts between neighboring regions.

Insulating regions anchor micromechanical stop structures on electrode surfaces, preventing electrical shorts and stabilizing components for sensors.

Projections on the superstrate body enhance crack propagation to resolve separation defects during whole wafer planarization.

Controlled surface roughness enables optical contact bonding for synthetic quartz substrates, eliminating thermal fusion defects.

Selective etching forms isolated nanodisks that resist thermal and magnetic instability in dense memory storage.

A multi-layer hard mask structure transfers patterns via selective etching to maintain uniform critical dimensions across device regions.

Dual-side electrode lead-out grooves in a MEMS micro mirror resolve the contradiction between wire bonding ease and wafer-level testing automation.

Selective SiO2 etching enables late-stage thinning to 20-200 μm, eliminating handling fragility and wafer bow during lithography.

Segmented release layers isolate substrate contact to prevent irregular transfer while maintaining high durability.

A decoration method applies a transparent varnish layer and prints adhesive patterns to attach metal foil selectively.