Parallel Releasing Structures for Narrow Gap Etching

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Solution Overview

Problem

The etching rate of narrow gaps in semiconductor devices is limited, leading to increased processing time and cost due to the restricted entry of etchants, which slows down the fabrication of semiconductor devices as feature sizes decrease.

Innovation Solution

The implementation of parallel releasing structures within the semiconductor substrate that abut the narrow gap, allowing simultaneous etching from multiple directions to remove the sacrificial material, thereby enhancing etching performance and reducing processing time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional single-direction etching is used for narrow gaps, then the etching process is simple to implement, but the etching rate is limited and processing time increases

Engineering Contradiction:
Improveetching rateVSAvoidstructure complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent divides the narrow gap into multiple segments by introducing parallel releasing structures that create multiple etching pathways. The single narrow gap is segmented into multiple sub-gaps, allowing etchants to access the sacrificial material from multiple directions simultaneously, thereby increasing the overall etching rate without requiring complex processing equipment.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from single-direction (one-dimensional) etching to multi-directional (three-dimensional) etching by introducing parallel releasing structures. This dimensional change allows etchants to approach the sacrificial material from multiple angles, dramatically improving etching efficiency while maintaining process simplicity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Manufacturing precision

If feature sizes are reduced to improve device integration, then device density increases, but etching access becomes more restricted and processing time increases

Engineering Contradiction:
Improvefeature size controlVSAvoidprocessing time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

By segmenting the narrow gap using parallel releasing structures, the patent enables etchants to access reduced-size features from multiple directions. This segmentation overcomes the access limitations imposed by smaller feature sizes, maintaining fast processing times even as device integration increases.

Inventive Principle:
Principle #1Segmentation

3Reliability

If narrow gap width is decreased to improve device performance, then device performance improves, but etchant entry is restricted and etching time increases

Engineering Contradiction:
Improvedevice performanceVSAvoidetching duration
Core Design Contradiction:
ReliabilityVSDuration of action of moving object

Solution Approach 1:

The patent uses parallel releasing structures to create multi-dimensional etching access to narrow gaps. This allows etchants to reach the sacrificial material in decreased-width gaps from multiple directions simultaneously, maintaining short etching durations even as gap width is reduced to improve device performance.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method significantly reduces the time required to remove sacrificial material from narrow gaps by enabling etchant access from multiple directions, improving etching efficiency and reducing the overall fabrication time and cost of semiconductor devices.

Implementation Method 1

Etching is a process by which material is removed from a semiconductor substrate to provide a topology that is used to form one or more layers on the semiconductor substrate.

Methodology Applied
Scientific EffectEtching:

Implementation Method 2

The etchant may comprise particles that react with an exposed surface of the semiconductor substrate.

Methodology Applied
Scientific EffectChemical reaction:

Implementation Method 3

a dry etchant may comprise energized particles which collide with an exposed surface of a semiconductor substrate to dislodge atoms from the exposed surface

Methodology Applied
Scientific EffectPhysical collision:

Data Source

PatentUS11018218B2Narrow gap device with parallel releasing structure
Publication Date: 2021.05.25 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11018218B2 patent drawing
  • US11018218B2 patent drawing
  • US11018218B2 patent drawing

AI summary

The present disclosure, in some embodiments, relates to a method of semiconductor processing. The method may be performed by etching a substrate to define a trench within the substrate. A sacrificial material is formed within the trench. The sacrificial material has an exposed upper surface. A plurality of discontinuous openings are formed to expose separate segments of a sidewall of the sacrificial material. The plurality of discontinuous openings are separated by non-zero distances along a length of the trench. An etching process is performed to simultaneously etch the exposed upper surface and the sidewall of the sacrificial material.