Semiconductor Fine Pattern Formation Using Multi-Layer Mask Etching
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Solution Overview
Problem
Current photolithography technologies face challenges in forming patterns with pitches smaller than the resolution limit of expositors, leading to misalignment and increased manufacturing costs due to the need for double patterning with multiple masks, which complicates the process and degrades throughput.
Innovation Solution
A method involving a stack layer of three mask films with different etching selectivity ratios, where a spin-on-carbon layer is used as an etching barrier to reduce the line-width of mask patterns, allowing for the formation of fine patterns with improved overlay alignment and simplified process steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If double patterning technology is used to form patterns with pitch smaller than resolution limit, then pattern formation capability is improved, but manufacturing cost increases and throughput decreases
Solution Approach 1:
The patent divides the patterning process into multiple stages using a three-layer mask structure (first mask film, second mask film, and third mask film). Each layer serves a specific function: the first and second mask films form initial patterns, while the third mask film enables further pattern division and refinement. This segmentation allows formation of sub-40nm patterns through controlled etching steps rather than requiring multiple separate lithography exposures, thereby improving throughput while maintaining manufacturing precision.
2Manufacturing precision
If double patterning technology is used to extend process margin, then resolution is improved, but overlay alignment deteriorates due to misalignment
Solution Approach 1:
The patent implements self-aligned patterning where the third mask film is positioned and etched based on the patterns already formed by the first and second mask films. The etching process automatically aligns subsequent patterns to the existing structure, eliminating the need for separate alignment steps between different lithography exposures. This self-service mechanism ensures consistent overlay alignment while achieving sub-40nm resolution.
3Productivity
If single exposure process is used, then throughput is maintained, but pattern line-width control deteriorates for patterns less than 40 nm
Solution Approach 1:
The patent transitions from two-dimensional planar patterning to three-dimensional vertical patterning by stacking multiple mask films at different heights. The first mask film forms initial patterns, the second mask film creates additional patterns at a different vertical level, and the third mask film enables further pattern refinement. This dimensional transition allows single-exposure lithography to achieve sub-40nm critical dimension control that would otherwise require multiple exposures, maintaining high throughput while improving manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the formation of patterns with reduced line-width and improved alignment, reducing manufacturing costs and increasing efficiency by simplifying the process, while achieving patterns that cannot be formed by current lithography equipment.
Implementation Method 1
The photoresist pattern is formed on the third mask film. The third mask films are etched with the photoresist pattern as an etching barrier mask to form third mask patterns.
Implementation Method 2
The second and first mask films are etched with the third mask patterns as an etching barrier mask to form a first and second mask pattern.
Implementation Method 3
The second mask pattern is side-etched with the third mask pattern as an etching barrier mask.
Implementation Method 4
A spin-on-carbon layer through which the upper portion of the second mask pattern is exposed is coated over first and second mask patterns and the underlying layer. A part of the first pattern and the second mask pattern are removed by the spin-on-carbon material as an etching barrier mask to expose the underlying layer.
Data Source
AI summary
A method for forming a fine pattern of a semiconductor device comprises forming a deposition pattern including first, second, and third mask patterns over a semiconductor substrate having an underlying layer, side-etching the second mask pattern with the third mask pattern as an etching barrier mask, removing the third mask pattern, forming a spin-on-carbon layer that exposes the upper portion of the second mask pattern, performing an etching process to expose the underlying layer with the spin-on-carbon layer as an etching barrier mask, and removing the spin-on-carbon layer.