Stackable Microelectronic Package Vertical Interconnects
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Solution Overview
Problem
Current microelectronic packaging technologies face challenges in reducing package size while maintaining electrical interconnection reliability.
Innovation Solution
The proposed solution involves a microelectronic assembly with a substrate having microelectronic elements spaced apart to create an interconnect area, where package terminals at one surface are electrically interconnected with substrate contacts, and stack terminals at the opposing surface are connected to form electrical connections with external components, allowing for the stacking of additional packages and enhanced interconnectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If microelectronic elements are mounted closely together on a substrate, then the package size is reduced, but electrical interconnection reliability deteriorates
Solution Approach 1:
The patent transitions from planar mounting to three-dimensional stacking by introducing vertical interconnections through the substrate. Multiple microelectronic elements are arranged in stacked layers and connected via vertical conductive pathways (through-substrate vias), enabling compact packaging while maintaining adequate electrical connection distances within each layer.
Solution Approach 2:
The package is divided into multiple functional layers, with microelectronic elements distributed across different levels. Each layer can be independently optimized for its specific function, and the vertical segmentation allows signal routing to be separated into horizontal (within-layer) and vertical (between-layer) components, improving overall interconnection reliability.
2Volume of moving object
If package size is reduced, then integration density is improved, but heat dissipation capability deteriorates
Solution Approach 1:
The patent introduces vertical thermal pathways through the substrate using the same through-substrate via structures that provide electrical interconnection. These vertical conduits create direct thermal conduction paths from upper layers to the substrate and ultimately to heat sinks, enabling efficient heat dissipation in the vertical dimension while maintaining compact horizontal footprint.
3Productivity
If multiple packages are stacked vertically, then integration density is improved, but manufacturing complexity deteriorates
Solution Approach 1:
The patent employs preliminary alignment features such as registration marks, alignment holes, and mechanical interlocking structures that are pre-formed during substrate fabrication. These features enable automated pick-and-place machinery to accurately position and stack packages without requiring complex real-time alignment systems, thereby reducing manufacturing complexity despite the increased integration density.
4Reliability
If interconnect area is increased for better electrical connections, then signal transmission quality is improved, but available space for microelectronic elements deteriorates
Solution Approach 1:
The patent moves interconnection functions from the horizontal plane to the vertical dimension by implementing through-substrate vias and vertical conductors. This allows signal transmission paths to extend through the substrate thickness, providing adequate electrical connection length and quality without consuming horizontal space that would be needed for mounting additional microelectronic elements.
Data Source
AI summary
A microelectronic assembly includes a first microelectronic package having a substrate with first and second opposed surfaces and substrate contacts thereon. The first package further includes first and second microelectronic elements, each having element contacts electrically connected with the substrate contacts and being spaced apart from one another on the first surface so as to provide an interconnect area of the first surface between the first and second microelectronic elements. A plurality of package terminals at the second surface are electrically interconnected with the substrate contacts for connecting the package with a component external thereto. A plurality of stack terminals are exposed at the first surface in the interconnect area for connecting the package with a component overlying the first surface of the substrate. The assembly further includes a second microelectronic package overlying the first microelectronic package and having terminals joined to the stack terminals of the first microelectronic package.