3D Semiconductor Circuit Atomic Switching Power Gating
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Solution Overview
Problem
The development of three-dimensional semiconductor integrated circuits faces challenges in reducing power consumption and improving performance, particularly in the back-end-of-line (BEOL) as the line width of wires approaches 250 nm, where the complexity and thermal density hinder advancements.
Innovation Solution
Integration of atomic switching elements within via-interconnections in the three-dimensional semiconductor integrated circuit, utilizing a driver circuit to selectively activate CMOS circuit blocks, reducing power consumption by acting as a power-gating element and enabling efficient signal transfer between CMOS circuit blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the line width of wires is reduced below 250 nm, then the transistor performance is improved, but the process difficulty and thermal density are increased
Solution Approach 1:
The patent transitions from two-dimensional planar transistors to three-dimensional vertically stacked transistors. Multiple transistor layers are stacked vertically, allowing increased effective channel width and improved performance without reducing the lithographic line width of individual wires. This dimensional change enables continued performance scaling while avoiding the process difficulties associated with sub-250 nm line widths.
2Use of energy by moving object
If atomic switching elements are integrated in via-interconnections, then power consumption is reduced, but the device structure becomes more complex
Solution Approach 1:
The patent merges the function of via-interconnections with atomic switching elements. The via holes that previously served only as passive conductive pathways are now integrated with atomic switching elements, combining interconnection and switching functions into a single structure. This reduces power consumption by enabling selective activation of circuit blocks while the driver circuit manages the increased structural complexity.
3Loss of energy
If atomic switching elements are used as power-gating elements, then power consumption during standby is reduced, but the manufacturing process becomes more complex
Solution Approach 1:
The patent implements preliminary action by pre-forming the atomic switching elements within the via holes during the fabrication process, before the devices are deployed. The solid electrolyte layers and electrode structures are prepared in advance during manufacturing, enabling the power-gating function to be activated later through electrical control without requiring additional manufacturing steps during operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption during circuit standby, enhances operating characteristics by uniformly controlling the size of conductive filaments, and integrates functional elements without occupying additional silicon area, thereby improving the performance and functionality of the BEOL.
Implementation Method 1
a solid electrolyte layer disposed between the non-active electrode and the active electrode
Implementation Method 2
enhances operating characteristics by uniformly controlling the size of conductive filaments
Data Source
AI summary
A three-dimensional semiconductor integrated circuit includes a first CMOS circuit layer including a plurality of first CMOS circuit blocks; an insulating layer disposed on a top of the first CMOS circuit layer; a plurality of atomic switching elements respectively disposed inside via holes extending through the insulating layer, wherein the plurality of atomic switching elements are electrically connected to the plurality of first CMOS circuit blocks, respectively; a driver circuit layer disposed on a top of the insulating layer, and electrically connected with the atomic switching elements, wherein the driver circuit layer include a driver circuit for selectively turning on and off the atomic switching elements; and a second CMOS circuit disposed on a top of the driver circuit layer and connected to the atomic switching elements.