Atomically Thin Fin Transistor for Sub-10 nm Integration
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Solution Overview
Problem
Current transistor technologies face challenges in reducing fin channel dimensions below 10 nm while maintaining good electrical properties and mechanical strength, which limits their integration density and sensitivity in applications like biological and gas sensors.
Innovation Solution
A method involving the formation of thin layers of two-dimensional semiconductor or semimetallic materials, such as graphene or transition metal dichalcogenides, on molding blocks, followed by selective removal to create fins with critical dimensions of less than 10 nm, allowing for independent control of fin dimensions and enhanced surface-to-volume ratio, and integration with source and drain electrodes for improved mechanical strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional lithography processes are used to reduce fin dimensions, then integration density improves, but manufacturing precision deteriorates due to inability to achieve dimensions below 10 nm
Solution Approach 1:
The patent changes the fundamental parameter for defining fin dimensions from lithographic patterning to atomic-layer deposition thickness. By controlling the number of atomic layers (1-10 layers) of two-dimensional semiconductor material, the fin critical dimension can be precisely controlled at sub-10 nm scale, bypassing lithography resolution limits while achieving atomic-level precision.
Solution Approach 2:
The patent transitions from planar lithographic patterning to vertical stacking of atomic layers. The fin dimension is no longer defined by lateral patterning but by the thickness of deposited atomic layers, effectively moving the control mechanism to a different dimensional regime (vertical deposition vs. lateral patterning).
2Productivity
If fin dimensions are reduced below 10 nm, then integration density improves, but electrical properties deteriorate due to quantum confinement and surface effects
Solution Approach 1:
The patent employs a composite structure where a thin layer of two-dimensional semiconductor material (such as MoS2, WS2, WSe2, or MoSe2) is deposited on a silicon fin. This hybrid structure combines the mechanical strength of silicon with the excellent electrical properties and atomic-thin profile of 2D semiconductors, maintaining good electrical performance even at sub-10 nm dimensions.
Solution Approach 2:
The patent changes the material composition parameter by introducing two-dimensional semiconductor materials with superior electrical properties. These materials have high carrier mobility and direct bandgap characteristics that maintain excellent electrical performance at atomic thickness, overcoming the quantum confinement effects that plague conventional silicon at similar dimensions.
3Productivity
If fin dimensions are reduced below 10 nm, then integration density improves, but mechanical strength deteriorates due to increased surface-to-volume ratio
Solution Approach 1:
The patent creates a composite structure where the two-dimensional semiconductor material forms an ultra-thin layer on the silicon fin surface. The bulk silicon provides the mechanical strength and structural integrity, while the 2D semiconductor layer provides the functional channel properties. This composite approach allows atomic-thin fins to maintain mechanical strength through the underlying silicon substrate.
Solution Approach 2:
The patent applies different materials with different properties to different regions: the bulk silicon fin provides mechanical strength, while the surface 2D semiconductor layer provides electrical functionality. This local differentiation allows the structure to simultaneously achieve atomic thickness for high integration density while maintaining mechanical strength through the supporting silicon substrate.
4Ease of manufacture
If conventional fin structures are used, then manufacturing is simplified, but sensor sensitivity deteriorates due to insufficient surface-to-volume ratio
Solution Approach 1:
The patent changes the fin dimension parameter to atomic thickness (1-10 atomic layers), which dramatically increases the surface-to-volume ratio. This extreme thinness maximizes the surface area available for interaction with analytes (biological or chemical species), thereby enhancing sensor sensitivity while maintaining a relatively simple manufacturing process based on atomic-layer deposition.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of transistors with extremely small fins that retain excellent electrical properties, suitable for high-sensitivity chemical and biological sensors, capable of detecting small quantities of substances, and offers improved detection sensitivity and reduced size.
Implementation Method 1
The thin layer is formed by catalytic growth, said one or more molding blocks being based on a catalytic material for the growth of said given material
Data Source
Figure 1A~1G
Figure 2A~2D
Figure 2E~3B
AI summary
Production of a transistor, the channel structure of which comprises at least one finned channel structure, the method comprising: - forming, from a substrate (1), a moulding block (3), - forming, on the moulding block, a fine layer (7) made from a given semiconductor or semi-metallic material, and consisting of one to ten atomic or molecular monolayers of two-dimensional crystal, - withdrawing the moulding block while retaining a portion (7a) of the fine layer extending against a lateral face of the moulding block, said retained portion (7a) forming a fin that is capable of forming a channel structure of the transistor, - producing a coating gate electrode against said fin.