At-Speed Test Clock Pulse Replay for Variable Capture Cycles
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Solution Overview
Problem
Conventional at-speed testing of integrated circuits is limited by a fixed number of clock pulses during the capture phase, restricting fault coverage and test quality, and cannot accommodate multi-load or RAM sequential patterns, while requiring large clocking systems due to stored configuration values for each frequency.
Innovation Solution
An electronic circuit board with a recording circuit and clocking system that records and replays clock pulses at the desired frequency, allowing variable clock pulses during the capture phase, controlled by the test circuit, enabling accurate at-speed testing and reducing system size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a fixed number of clock pulses is used during the capture phase, then the clocking system can be simplified, but fault coverage and test quality are restricted
Solution Approach 1:
The patent implements a dynamic clock pulse generation system where the number of clock pulses during the capture phase is no longer fixed but can be varied based on test requirements. The test controller dynamically adjusts the clock pulse count to accommodate different test patterns (such as multi-load or RAM sequential patterns) while maintaining system simplicity through automated control.
2Adaptability or versatility
If configuration values for each frequency are stored in the clocking system, then frequency switching is enabled, but the system size increases
Solution Approach 1:
The patent uses a test controller that generates test clock signals externally, copying the functionality of the internal clocking system. Instead of storing configuration values for each frequency in the IC, the external test controller generates the appropriate clock signals, thereby reducing the internal clocking system size while maintaining frequency switching capability.
3Stability of the object's composition
If the test circuit generates test patterns in-line with a fixed number of clock pulses, then synchronization is maintained, but test quality and fault coverage are limited
Solution Approach 1:
The patent implements dynamic control of clock pulse generation during the capture phase, allowing the number of clock pulses to vary based on test requirements. The test controller dynamically adjusts the clock pulse count while maintaining synchronization through controlled generation, enabling support for complex test patterns like multi-load or RAM sequential patterns that require variable clock cycles.
Data Source
AI summary
An integrated circuit (IC), including a recording circuit and a clocking system, is provided. During a capture phase of an at-speed testing of the IC, the recording circuit records a number of clock pulses of a test clock signal and generates configuration data indicative of the recorded number of the clock pulses. The clocking system receives a reference clock signal and the configuration data and generates an at-speed clock signal. During the capture phase, the at-speed clock signal includes clock pulses that are extracted from the reference clock signal based on the configuration data. A count of the extracted clock pulses is equal to the recorded number of clock pulses of the test clock signal. The at-speed testing of the IC is enabled based on the at-speed clock signal.