Au Bump Via for Semiconductor Chip Electrical Connection
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Solution Overview
Problem
Conventional semiconductor chip manufacturing processes incur increased costs and complexity due to the use of conductive metal members and metal layers for connecting electrode pads with through vias, which also lead to potential voids in the through vias during the electroplating process.
Innovation Solution
The use of Au bumps deposited on electrode pads and through vias to establish electrical connections, reducing the depth of through holes and simplifying the manufacturing process, while employing wire bonding technology and electroplating with Au bumps as a power feeding layer to prevent voids in the through vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive metal members and metal layers are provided to electrically connect the electrode pad with the through via, then electrical connection is achieved, but manufacturing cost increases
Solution Approach 1:
The patent merges the functions of the conductive metal member and the metal layer into a single integrated structure. The through via is formed to penetrate through both the electrode pad and the conductive metal member, eliminating the need for separate metal layers and reducing manufacturing steps while maintaining electrical connection reliability
Solution Approach 2:
The patent extracts and eliminates the redundant metal layer from the conventional structure. By designing the through via to directly penetrate through the electrode pad and conductive metal member, the unnecessary metal layer is removed, simplifying the manufacturing process and reducing costs
2Reliability
If conductive metal members and metal layers are provided to electrically connect the electrode pad with the through via, then electrical connection is achieved, but process complexity increases
Solution Approach 1:
The patent combines multiple manufacturing steps into a simplified process. The through via is formed in a single penetrating operation through both the electrode pad and conductive metal member, eliminating the need for separate metal layer formation and reduction steps, thereby reducing process complexity
3Reliability
If the through hole is deepened to accommodate the conductive metal member, then electrical connection is achieved, but electroplating time increases
Solution Approach 1:
The patent removes the redundant metal layer that caused the through hole to be unnecessarily deep. The through via is formed to penetrate only through the electrode pad and conductive metal member, reducing the hole depth and consequently shortening the electroplating time required
4Reliability
If the through via is formed by deposition and growth of conductive metal on the metal layer, then electrical connection is achieved, but voids are created in the through via
Solution Approach 1:
The patent extracts and eliminates the metal layer that served as the base for conductive metal deposition. By forming the through via to penetrate through the electrode pad and conductive metal member without relying on metal layer deposition, the process that caused void formation is completely removed
Solution Approach 2:
Instead of forming the through via by depositing conductive metal on a metal layer (bottom-up approach), the patent inverts the approach by forming the through via to penetrate through existing structures (top-down approach), thereby avoiding void formation associated with deposition processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs, simplifies the process, and prevents voids in the through vias, resulting in a more cost-effective and efficient semiconductor chip production.
Implementation Method 1
The through via 111 is formed by use of an electroplating method for which the metal layer 108 is used as a power feeding layer
Implementation Method 2
employing wire bonding technology and electroplating with Au bumps as a power feeding layer to prevent voids in the through vias
Data Source
AI summary
A semiconductor chip includes a semiconductor substrate having a first principal surface, and having a device layer on the first principal surface in which a semiconductor device is formed, an electrode pad disposed on the first principal surface of the semiconductor substrate and electrically connected to the semiconductor device, a through via formed in a through hole penetrating through the semiconductor substrate and the electrode pad, and an Au bump deposited on the electrode pad and the through via such as to electrically connect between the electrode pad and the through via.