Audio Output Clock Recovery With Multi-Stage Division and Phase Tuning
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Solution Overview
Problem
Existing HDMI clock signal recovery methods face challenges in achieving high accuracy due to the large values of parameters N and CTS, and are prone to noise interference, making it difficult to perform frequency-division operations effectively.
Innovation Solution
The proposed solution involves using multiple frequency dividers with dynamic phase adjustment and a fine tuning circuit to improve accuracy and noise resistance, allowing for more precise generation of an audio output clock signal by dividing the video clock signal through frequency-division factors K, M, and SF, and adjusting the phase to match the audio clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If frequency-division operations are performed using large parameter values (N≈11648, CTS=tens of thousands to hundreds of thousands), then measurement precision of clock frequency is improved, but device complexity and susceptibility to noise interference increase
Solution Approach 1:
The patent segments the frequency-division operation into multiple stages using different dividers (first frequency divider with division ratio N1, second frequency divider with division ratio N2, third frequency divider with division ratio N3). This breaks down the complex single-stage division by large parameters into simpler sequential stages, reducing computational complexity while maintaining precision.
Solution Approach 2:
The patent introduces dynamic phase adjustment mechanisms including a phase adjusting circuit that dynamically adjusts phase of clock signals and a fine tuning circuit that dynamically adjusts division ratios based on feedback. This allows the system to adapt to noise and maintain accuracy without requiring static high-precision dividers.
2Measurement precision
If frequency-division operations use large parameter values (N≈11648, CTS=tens of thousands to hundreds of thousands), then measurement precision of clock frequency is improved, but reliability under noise interference deteriorates
Solution Approach 1:
By dividing the frequency division into multiple stages with smaller division ratios (N1, N2, N3) rather than single large ratios, each stage is less susceptible to noise accumulation. The segmented approach allows intermediate signals to be more robust and easier to filter.
Solution Approach 2:
The patent implements feedback mechanisms where a phase detector detects phase differences between clock signals and feeds this information to the phase adjusting circuit and fine tuning circuit. This closed-loop feedback continuously compensates for noise-induced deviations, maintaining reliability under interference.
3Measurement precision
If phase-locked loop with frequency divider is used to derive clock signals, then frequency accuracy is improved, but device complexity and noise susceptibility increase
Solution Approach 1:
The patent segments the PLL functionality across multiple components: phase detector, controlled oscillator, phase adjusting circuit, and multiple frequency dividers. This modular segmentation makes the complex PLL design more manageable and implementable with standard circuit blocks.
Solution Approach 2:
The patent introduces dynamic phase adjustment circuits that actively modify phase relationships in real-time based on detected errors. This dynamic adjustment simplifies the overall design by providing flexibility to achieve frequency accuracy without requiring ultra-precise static divider ratios.
4Measurement precision
If dynamic phase adjustment and fine tuning circuits are added to improve accuracy, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent uses dynamic phase adjustment circuits and fine tuning mechanisms that actively adapt to maintain accuracy. These dynamic elements provide precision without requiring overly complex static circuit design, as the adjustment happens operationally based on feedback.
Solution Approach 2:
The fine tuning circuit receives feedback about phase and frequency deviations and makes real-time adjustments to division ratios and phase shifts. This feedback-driven approach achieves high precision through simple adaptive adjustments rather than complex predetermined circuitry.
Data Source
AI summary
An apparatus for generating an audio output clock is disclosed. The apparatus at least includes a plurality of dividers and a frequency synthesizer. The apparatus utilizes the dividers to achieve dispersive frequency-division operations such that the anti-noise ability of the apparatus can be improved. In addition, the apparatus also utilizes dynamic phase adjustment to increase accuracy of the frequency of the audio output clock.