Partitioned Audio Converter Interface for Lower Pin-Count Wiring
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Solution Overview
Problem
Conventional signal processing systems for multimedia in electronics, such as mobile phones and digital cameras, face challenges with high pin-count and complex inter-chip wiring due to the use of I2S and Slimbus for inter-chip communication, which increase implementation costs and hardware complexity.
Innovation Solution
A signal processing system is distributed across two chips, with each converter partitioned into two portions, one on each chip, using sigma-delta modulation and up-sampling/down-sampling filters to optimize circuit layout area, pin-count, and inter-chip communication throughput, allowing for flexible frequency interfaces and reduced pin-count through efficient inter-chip connection circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If I2S bus is used for inter-chip communication, then digital audio signal transmission is achieved, but pin-count and inter-chip wiring complexity increase
Solution Approach 1:
The codec chip is divided into two separate chips: a digital chip containing digital signal processing functions and an analog chip containing DAC/ADC and analog output functions. This segmentation allows the digital chip to use fewer pins for communication while the analog chip handles the complex analog conversions, thereby reducing overall pin-count and wiring complexity while maintaining reliable digital audio transmission.
Solution Approach 2:
A dedicated digital interface circuit is introduced as an intermediary between the main chip and the analog chip. This interface circuit manages the digital audio signal transmission efficiently, reducing the burden on the main chip's pin-count and simplifying the inter-chip wiring while ensuring reliable signal transmission.
2Adaptability or versatility
If more audio channels are supported, then audio functionality is improved, but pin-count and wiring complexity increase
Solution Approach 1:
Multiple audio channel processing functions are merged into the digital signal processing circuit on the digital chip. The digital chip handles all digital signal processing for multiple channels, while the analog chip performs unified DAC conversion. This merging approach allows multiple audio channels to be supported without proportionally increasing pin-count and wiring complexity.
3Adaptability or versatility
If DAC and ADC are integrated into a single codec chip, then signal processing functionality is improved, but circuit layout area increases
Solution Approach 1:
The codec functionality is segmented into two separate chips: a digital chip for digital signal processing and an analog chip for DAC/ADC. This segmentation reduces the circuit layout area of each individual chip compared to a single integrated codec chip, while maintaining complete signal processing functionality across the two-chip system.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes implementation costs by reducing pin-count and hardware complexity while maintaining high throughput and flexibility in signal processing, enabling efficient digital-to-analog and analog-to-digital conversions across the chips.
Implementation Method 1
DAC and/or ADC can be implemented by sigma-delta modulation along with multiple up-sampling filters and/or down-sampling decimators which convert between different frequencies
Data Source
AI summary
The present invention provides a signal processing system and associated method. The signal processing system includes converter(s) for conversion between digital and analog, each converter includes multiple serially coupled units forming multiple frequency interfaces respectively associating with different frequencies, and each converter is partitioned, at a selected frequency interface, to a first portion and a second portion respectively formed in the first chip and the second chip. The partitioning frequency interface is selected to reduce implement cost.