Analogue Conversion TRIZ Cases

Quantizer-driven pre-charging cuts input-node current in a delta-sigma ADC, enabling high-impedance sensor inputs without buffers.

Programmable ELD compensation and integrator bypass paths let a continuous-time ADC cut power while preserving stability across bandwidth modes.

A split ADC architecture uses a first-order analogue filter and digital noise shaping to keep high dynamic range stable at low power.

Adjustable clock delay and loop filter bandwidth let a CTDSM ADC preserve stability and noise shaping across multiple sampling rates.

A segmented DAC combines an R-2R stage, interpolation DAC, and Sigma Delta modulation to cut area, power, and calibration memory.

Decreasing cycle weights and shorter conversion phases improve sigma-delta linearity at lower OSR without significantly raising noise.

Multiple sampling with feedback and filtering helps a quantizing circuit resolve small noisy signal differences in multi-bit memory reads.

Simultaneous sigma-delta sampling of self, mutual, and pen signals cuts touch sample time while improving noise rejection and accuracy.

One-bit delta-sigma current processing improves time resolution for synchronized control loops while reducing filter hardware burden.

Duty-cycle detection and sample-and-hold preserve speaker voltage estimates during class-D amplifier clipping without a separate measurement channel.

Matching charge pump switching to a delta-sigma noise-transfer zero cuts audio distortion while digital filters flatten passband droop.

Lowering the modulation clock and redistributing loop gain cuts delta sigma modulator power while preserving the loop transfer function.

Alternating even- and odd-phase input/output switching averages digital offset codes to cut transistor mismatch errors without slowing analog circuits.

An internal detector and compensator correct pulse asymmetry inside a delta-sigma modulator to reduce target-frequency distortion.

Impedance circuits shift forward-path zeros in a continuous-time sigma-delta modulator to suppress out-of-band peaking and protect dynamic range.

Two modulation stages and an analog high-pass filter reshape quantization noise to raise SNR while reducing power and circuit area.

Automatic gain compensation boosts weak high-frequency pacer signal SNR while preserving low-frequency ECG quality and correcting settling artifacts.

A crossbar switch matrix generates DWA from thermometric code, removing decoder and adder delay, power, and area overhead.

A DAC-amplifier feedback loop stabilizes high-current TOF illumination at high modulation frequencies while reducing phase noise and power use.

A linearized summer circuit buffers sampler nodes and stabilizes output impedance to cut differential kickback noise at high data rates.

Period-synchronous digital averaging filters periodic disturbance peaks while reducing measurement delay for more stable control loops.

A first-stage digital correction signal cancels feedback DAC mismatch in MASH ADCs, improving high-speed linearity and SNDR.

Slew-controlled voltage pulses decouple DAC current pulse timing from clock jitter, improving feedback accuracy without high-bandwidth amplifiers.

Bit swapping after parallel-to-serial conversion cuts pulse edges in switching amplifiers, preserving high SNR with lower power loss.

A correction path outside the feedback loop compensates quantizer metastability errors to improve Sigma-Delta ADC SNR and dynamic range.

Quantization noise analysis checks ADC health in real time by comparing spectral and pulse-width patterns to detect failures accurately.

Preconfigured capacitor branches and amplifier paths cut analog reconfiguration time while improving noise rejection, signal fidelity, and power use.

Interleaved gain stages and sequential switching cut metastability and offset errors in high-speed sigma-delta modulators.

A voltage comparator replaces LED-based level sensing to improve digital signal level conversion accuracy and support wider chip interface ranges.

Oversampling image sensing with sigma-delta conversion suppresses DC components, cuts modulator complexity, and improves holographic SNR.

Two-phase sampling with cyclic capacitor rotation cancels sigma-delta gain error while doubling throughput or reducing amplifier bandwidth.

Square-wave up-conversion plus digital sine down-conversion suppresses sensor noise and offset with lower analog circuit complexity.

A negative capacitor at the quantizer input cancels parasitic capacitance and extra poles, improving delta-sigma modulator stability.

Charge-error integration with radix-based feedback pulses expands focal plane ADC dynamic range while reducing area and power.

A shared amplifier alternates between two delta-sigma modulators to cut ADC power use while preserving high SNR in multi-channel conversion.

A hybrid analog-digital MASH ADC processes noise contribution signals to improve SNR and dynamic range without high-order modulator instability.

Signal-path shuffling enables background comparator offset calibration in delta-sigma ADCs, reducing quantization noise without interrupting operation.

Adaptive chopping and dynamic element matching balance analog noise and distortion by changing reduction rates with signal amplitude.

Parallel charge amplifiers and modulators feed a shared residue ADC to measure more electrodes with higher capacitive sensing accuracy.

Partitioning DAC and ADC functions across two chips cuts inter-chip pin-count and wiring complexity while preserving high-throughput audio conversion.

Reference voltage tuning lets a sigma-delta converter switch between narrowband low-noise and broadband high-speed modes with fewer capacitors.

A single-voltage calibration scheme measures real delta-sigma ADC gain through switched-capacitor feedback, reducing reference complexity and error.

Pre-charging the sampling capacitor through a voltage buffer limits transient and ESD current at ADC inputs while preserving linearity.