Phase-Switched Analog Circuits for Transistor Mismatch Offset Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Random offsets caused by transistor random mismatch in analog circuits, such as operational amplifiers, comparators, and converters, affect circuit performance significantly and existing methods like auto zero are limited in application and speed.
Innovation Solution
A system and method using a digital means with a phase controller and switches to alternate input and output connections between pairs of matching transistors during even and odd phases, allowing for averaging of digital codes to reduce random offsets, applicable to circuits like DACs, ADCs, and comparators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If auto zero method using capacitor is used to reduce random offsets, then offset reduction is achieved, but circuit speed is limited due to required equilibration phase
Solution Approach 1:
The patent replaces the traditional analog auto-zero method (using capacitors and equilibration phases) with a digital calibration approach. The system uses digital codes to represent offset values and performs calibration through digital processing, eliminating the need for analog equilibration phases and thereby increasing circuit speed while maintaining offset reduction capability
Solution Approach 2:
The patent changes the operational parameters by introducing multiple calibration phases (first calibration phase, second calibration phase, third calibration phase) with different switching configurations. By varying the phase timing and switching states, the system achieves offset cancellation without requiring lengthy equilibration periods, thus improving both precision and speed
2Measurement precision
If auto zero method is applied, then random offsets are reduced, but application is limited to certain circuits
Solution Approach 1:
The patent creates a universal calibration system that can be applied to multiple circuit types including operational amplifiers, comparators, current mirrors, analog-to-digital converters, and digital-to-analog converters. The system uses configurable switches (first switches, second switches) and phase controllers that can be adapted to different circuit architectures, making the offset reduction method broadly applicable across various analog and mixed-signal circuits
3Speed
If digital calibration with phase controller is used, then circuit speed is improved, but device complexity increases
Solution Approach 1:
The patent segments the calibration process into distinct phases (first calibration phase, second calibration phase, third calibration phase) with dedicated switching networks for each phase. By dividing the overall calibration function into smaller, manageable segments with specific switching configurations, the system achieves high-speed operation while making the complexity modular and controllable
Data Source
AI summary
An analog circuit including a pair of input nodes and a pair of output nodes is coupled to a mismatch reduction circuit including an input node, an output node, a phase controller that times even and odd phases, an input switch, and an output switch. The input switch electrically connects the mismatch reduction circuit input node to a first node of the pair of analog circuit input nodes during each even phase and to electrically connects the mismatch reduction circuit input node to a second node of the pair of analog circuit input nodes during each odd phase. The output switch electrically connects a first node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each even phase and electrically connects a second node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each odd phase.