Sigma-Delta Modulator Gain Calibration With Two-Phase Capacitor Rotation
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Solution Overview
Problem
Sigma-delta modulators face limitations in achieving fast sampling rates with low gain error due to the need for four phases per sample, which increases power consumption and reduces efficiency.
Innovation Solution
A sigma-delta modulator design that uses only two phases per sample by sampling DAC signals and input signals in parallel on different capacitor pairs, with a rotation algorithm to average mismatch errors and maintain a low gain error, achieving a scaling factor of S/R while reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If four phases per sample are used to achieve low gain error through capacitor rotation, then gain error accuracy is improved, but power consumption increases and throughput rate decreases
Solution Approach 1:
The capacitor array is divided into multiple groups that can be independently controlled and rotated. By segmenting the capacitors into groups and using rotation algorithms, the patent achieves gain error cancellation through averaging mismatch errors across different capacitor groups, while requiring only two phases per sample instead of four, thus reducing power consumption.
Solution Approach 2:
The patent employs periodic rotation of capacitor groups across multiple samples. The rotation algorithm cyclically assigns different capacitor groups to sample the input signal and DAC voltage, creating a periodic pattern that averages out mismatch errors over time. This periodic action achieves low gain error without requiring four phases per sample.
2Measurement precision
If four phases per sample are used to rotate capacitor pairs for gain error cancellation, then gain error accuracy is improved, but throughput rate decreases
Solution Approach 1:
By segmenting capacitors into multiple rotatable groups, the patent enables gain error cancellation to be achieved across multiple samples rather than requiring four phases within a single sample. This segmentation approach allows one phase per sample to be sufficient, doubling the throughput rate while maintaining ppm-level gain error accuracy through the rotation algorithm.
Solution Approach 2:
The rotation algorithm continues to average mismatch errors across multiple consecutive samples, maintaining continuous gain error cancellation. This continuous action across samples achieves the same accuracy as four-phase methods but at half the time cost, effectively doubling the throughput rate.
3Measurement precision
If capacitor rotation algorithm is applied across multiple samples, then gain error is reduced to low ppm levels, but device complexity increases
Solution Approach 1:
The patent divides capacitors into manageable groups with simple rotation patterns. Each group can be controlled independently with basic switching logic, reducing the overall control complexity compared to managing all capacitors simultaneously. The segmentation enables the rotation algorithm to be implemented with modest control overhead while achieving low ppm-level gain error.
4Productivity
If two phases per sample are used instead of four, then throughput rate doubles, but gain error increases without rotation algorithm
Solution Approach 1:
The patent implements a periodic rotation algorithm that cycles through different capacitor groups across multiple samples. This periodic action averages the mismatch errors over time, achieving low gain error even with only two phases per sample. The periodic rotation compensates for the reduced phase count while maintaining ppm-level accuracy.
Solution Approach 2:
The rotation algorithm uses feedback from multiple samples to continuously average and cancel gain errors. By monitoring the DAC voltage and input signal across successive samples and adjusting capacitor group assignments accordingly, the system maintains low gain error despite operating in only two phases, thus achieving both high throughput and high accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach doubles the throughput rate or halves the bandwidth requirements for amplifiers, reducing power usage and achieving low ppm-level gain error accuracy, allowing continuous gain error cancellation within the conversion process.
Implementation Method 1
a chopper voltage reference providing a reference signal having a clock dependent offset voltage
Implementation Method 2
The input and DAC voltage are sampled on capacitors (or pairs of capacitors for differential voltages) inside the loop filter of the delta-sigma modulator
Data Source
Figure 1A~1B
Figure 2
Figure 3A
AI summary
A sigma-delta modulator has a chopper voltage reference providing a reference signal having a clock dependent offset voltage, a single-bit or a multi-bit digital-to-analog converter (DAC); a plurality of capacitor pairs; a plurality of switches to couple any capacitor pair to an input or reference signal; and a control unit controlling sampling through said switches to perform a charge transfer in two phases wherein any capacitor pair can be selected to be assigned to the input or reference signal, wherein after a plurality of charge transfers a gain error cancellation is performed by rotating the capacitor pairs cyclically, and wherein a DAC output value and a reference offset state define switching sequences wherein each switching sequence independently rotates said capacitor pairs and wherein at least one switching sequence is selected depending on a current DAC output value and a current reference offset state.