Logarithmic ADC Feedback Circuit for Wide Dynamic Range Imaging
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current analog to digital converters in focal plane arrays face challenges with high dynamic range, leading to increased power consumption, larger area, and slower frame rates due to the dominant size of counters and the need for more bits to handle scene offset charge, which results in inefficient integration time and signal to noise ratio.
Innovation Solution
A logarithmic analog to digital converter (LADC) with an error integration circuit, quantizer, accumulator, and charge feedback device that integrates input charge with feedback pulses to create an error voltage, allowing for a logarithmic response that digitizes a larger dynamic range with lower power consumption and maintaining signal to noise and distortion ratio over multiple octaves.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional analog to digital converters are used to handle high dynamic range, then the dynamic range coverage is improved, but the counter size increases linearly with dynamic range leading to larger area and higher power consumption
Solution Approach 1:
The patent transforms the linear conversion process into a logarithmic one by changing the mathematical parameter of the conversion function. The error integration circuit integrates the difference between input charge and feedback charge pulses on a logarithmic scale, allowing the converter to handle high dynamic ranges with constant area and power consumption, resolving the contradiction between dynamic range coverage and converter area.
2Measurement precision
If more bits are used to handle scene offset charge, then the dynamic range capability is improved, but the counter size and power consumption increase
Solution Approach 1:
The patent changes the operational parameter from linear counting to logarithmic integration. The error integration circuit accumulates charge differences in a logarithmic manner, which allows representing a wide dynamic range using fewer bits, thereby reducing power consumption while maintaining dynamic range capability.
Solution Approach 2:
The patent implements a feedback mechanism where feedback charge pulses are generated based on the accumulated error and fed back to the error integration circuit. This closed-loop feedback system allows the converter to adapt to the input signal level dynamically, maintaining high dynamic range capability with reduced bit requirements and lower power consumption.
3Measurement precision
If single capacitor is sized for smallest least significant bit, then the conversion precision is improved, but the integration time becomes proportional to the larger dynamic range instead of signal to noise ratio
Solution Approach 1:
The patent introduces dynamic adaptation into the integration process. The error integration circuit dynamically adjusts its operation based on the input signal level and the accumulated error, allowing the integration time to be proportional to the signal-to-noise ratio rather than the full dynamic range. This dynamic behavior resolves the contradiction between conversion precision and integration time.
Data Source
AI summary
An analog to digital converter includes an error integration circuit configured to receive an input charge from a detector and to integrate a difference between the input charge and one or more feedback charge pulses to create an error voltage. A quantizer is in operable communication with the error integration circuit and is responsive to the created error voltage. An accumulator having a mantissa component and a radix component is in operable communication with the quantizer. A charge feedback device in operable communication with the quantizer and the radix component of the accumulator. The charge feedback device is configured to generate the one or more feedback charge pulses proportional to the radix component of the accumulator and an output of the quantizer. Digital focal plane read out integrated circuits including the analog to digital converter are also disclosed.