Split-Architecture ADC for Stable High Dynamic Range
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Solution Overview
Problem
Existing analogue to digital converters (ADCs) face challenges in maintaining stability and low power consumption across varying sample rates, particularly in applications requiring high dynamic range and flexibility, such as speech/voice-band processing and high-end audio, while minimizing analogue circuitry and power dissipation.
Innovation Solution
The design incorporates a split architecture with a first-order analogue filter and a multi-bit digital integrator, along with a second-order digital sigma delta modulator block, allowing for scalability and stability across different sample rates, and includes a finite impulse response digital to analogue converter for multi-level feedback, reducing power dissipation through optimized oversampling ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the ADC uses a conventional architecture with extensive analogue circuitry to achieve high dynamic range, then the resolution and dynamic range are improved, but the power consumption increases
Solution Approach 1:
The patent replaces extensive analogue circuitry with digital components. The analogue filter is retained but followed by digital processing stages including a digital integrator and digital sigma-delta modulator, substituting analogue amplifiers and filters with digital logic to reduce power consumption while maintaining high dynamic range performance
Solution Approach 2:
The patent changes the operating parameters by using oversampling at a higher rate than the output sample rate, allowing the use of a simpler first-order analogue filter followed by digital processing. This parameter change (oversampling ratio) enables reduction of analogue circuit complexity and power consumption while achieving the required dynamic range through digital noise shaping and filtering
2Speed
If the ADC is designed for high sample rates to improve processing speed, then the bandwidth is improved, but the power consumption increases
Solution Approach 1:
The patent segments the conversion process into distinct stages: a first-order analogue filter for initial signal conditioning, a quantizer for digital conversion, a digital integrator for noise shaping, and a digital sigma-delta modulator for final processing. This segmentation allows each stage to operate at optimized rates, with digital stages handling high-speed processing with low power consumption compared to equivalent analogue circuitry
Solution Approach 2:
The patent substitutes analogue signal processing circuitry with digital processing stages. The digital integrator and digital sigma-delta modulator blocks perform functions that would traditionally require high-speed analogue circuitry, but implement them using low-power digital logic, thereby achieving high effective sample rates without proportional increases in power consumption
3Device complexity
If the ADC uses a first-order analogue filter to reduce analogue circuitry, then the device complexity is reduced, but the resolution may be insufficient
Solution Approach 1:
The patent compensates for the limited filtering capability of a first-order analogue filter by substituting digital processing stages. The digital integrator and digital sigma-delta modulator perform noise shaping and filtering in the digital domain, achieving high resolution (e.g., 110 dB dynamic range) without requiring complex higher-order analogue filters, thus maintaining low device complexity while achieving high precision
Solution Approach 2:
The patent moves the filtering and precision-enhancing functions from the analogue domain to the digital domain. By implementing noise shaping and filtering in the digital dimension rather than requiring complex analogue filter structures, the system achieves high resolution with minimal analogue circuitry, effectively trading analogue complexity for digital processing
Data Source
Figure 1~2a
Figure 2b
AI summary
An analogue to digital converter comprises an input terminal configured to receive an analogue input signal and an output terminal configured to provide an output digital signal. The analogue to digital converter also comprises a main summer having a summing input, a subtracting input and a summing output, wherein the summing input is connected to the input terminal; an analogue filter having a filter input and a filter output, wherein the filter input is connected to the summing output; a quantizer having a quantizer input and a quantizer output, wherein the quantizer input is connected to the filter output;a digital integrator having a digital integrator input and a digital integrator output, wherein the digital integrator output is configured to provide a multi-bit output signal, the digital integrator input is connected to the quantizer output, and the digital integrator output is connected to the output terminal; and a main feedback digital to analogue converter having a main feedback converter input and a main feedback converter output, wherein the main feedback converter input is connected to the digital integrator output, and the main feedback converter output is connected to the subtracting input of the main summer.