Segmented DAC Calibration With R-2R and Interpolation Stages
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Solution Overview
Problem
High-accuracy digital-to-analog converter (DAC) circuits require significant circuit area and increased calibration memory, leading to higher power consumption and longer calibration times due to the need for numerous switches and resistor elements, especially in applications like medical devices and industrial control systems.
Innovation Solution
The development of segmented DAC circuits that utilize a resistor DAC for the most significant bit, an interpolation DAC for offsetting, and a Sigma Delta modulator, along with a calibration method that measures output voltages for subwords and calculates calibration codes to minimize the number of switches and memory requirements, using a resistor-two-resistor (R-2R) DAC and ordered element matching (OEM) circuits to achieve high accuracy with reduced components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional high-accuracy DAC circuits are used, then conversion accuracy is improved, but circuit area increases significantly
Solution Approach 1:
The patent divides the DAC circuit into three independent sub-DACs: MSB sub-DAC (most significant bits), ISB sub-DAC (intermediate significant bits), and LSB sub-DAC (least significant bits). Each sub-DAC handles a specific bit range, allowing parallel operation with fewer total components than a traditional single DAC would require for the same resolution. This segmentation reduces circuit area while maintaining high conversion accuracy.
2Measurement precision
If traditional high-accuracy DAC circuits are used, then conversion accuracy is improved, but power consumption increases
Solution Approach 1:
By segmenting the DAC into three sub-DACs that operate in parallel, each handling a specific bit range, the patent reduces the total number of switches and resistor elements required compared to a traditional single high-resolution DAC. Fewer active components result in lower overall power consumption while achieving the same conversion accuracy.
3Measurement precision
If traditional high-accuracy DAC circuits are used, then conversion accuracy is improved, but calibration memory requirements increase
Solution Approach 1:
The calibration process is segmented into three independent calibration procedures, one for each sub-DAC (MSB, ISB, and LSB). Each sub-DAC is calibrated separately using its own calibration code stored in dedicated calibration memory. This segmentation reduces the total calibration memory requirement compared to calibrating a single high-resolution DAC, as each sub-DAC requires calibration memory proportional to its own resolution rather than the full resolution.
4Measurement precision
If traditional high-accuracy DAC circuits are used, then conversion accuracy is improved, but calibration time increases
Solution Approach 1:
The calibration process is divided into three independent parallel calibration operations for the MSB, ISB, and LSB sub-DACs. Since these calibrations can be performed independently and simultaneously, the total calibration time is significantly reduced compared to sequential calibration of a traditional single DAC, while still achieving high conversion accuracy through the combined output of all three sub-DACs.
5Measurement precision
If the number of switches and resistor elements is increased, then DAC accuracy is improved, but device complexity increases
Solution Approach 1:
The patent reduces device complexity by segmenting the high-resolution DAC into three lower-resolution sub-DACs. Each sub-DAC requires fewer switches and resistor elements than a single high-resolution DAC would require. The parallel architecture of the three sub-DACs achieves the same overall accuracy with fewer total components, thereby reducing device complexity.
Data Source
AI summary
Disclosed examples include a segmented DAC circuit, including an R-2R resistor DAC to convert a first subword to a first analog output signal, an interpolation DAC to offset the first analog output signal based on an N-bit digital interpolation code signal to provide the analog output signal, and a Sigma Delta modulator to modulate a modulator code to provide the N-bit digital interpolation code signal that represents a value of second and third subwords.