CTDSM ADC Clock Delay Compensation for Scalable Sampling Rates
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Solution Overview
Problem
Continuous-time delta-sigma modulator (CTDSM) analog-to-digital converters suffer from excess loop delay (ELD), which degrades their stability and requires flexible compensation methods to accommodate varying loop bandwidths and sampling rates, but conventional solutions are inflexible and limit the number of supported sampling rates.
Innovation Solution
The implementation of a CTDSM ADC with scalable sampling rates and ELD compensation, achieved through a loop filter, quantizer, DACs, and a clock delay circuit, allowing for dynamic adjustment of sampling frequency, clock delays, and amplifier bandwidth to maintain stability across different configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional ELD compensation methods are used, then ADC stability is maintained, but the number of supported sampling rates is limited
Solution Approach 1:
The patent changes parameters of existing components (clock delay, amplifier bandwidth) to accommodate different sampling rates without adding new compensation paths. Specifically, the clock delay circuit adjusts its delay parameter and the loop filter adjusts its amplifier bandwidth parameter dynamically, allowing the same hardware structure to support multiple sampling rates while maintaining ELD compensation effectiveness
Solution Approach 2:
The patent introduces dynamic adjustability to static components. The clock delay circuit and loop filter amplifier bandwidth are made dynamically可调 (adjustable) rather than fixed, enabling the system to adapt to different sampling rates. This dynamic behavior allows a single compensation path to serve multiple operating conditions, resolving the contradiction between versatility and complexity
2Productivity
If sampling frequency is increased, then ADC productivity improves, but excess loop delay degrades stability
Solution Approach 1:
The patent applies preliminary compensation action by introducing a clock delay circuit that proactively compensates for the excess loop delay before it degrades stability. The delay circuit is designed to provide the exact compensation needed for the maximum sampling rate, and this compensation remains effective at lower sampling rates as well, allowing the system to operate at high productivity levels while maintaining reliability
Solution Approach 2:
The patent applies preliminary anti-action by introducing a compensatory delay that counteracts the harmful excess loop delay effect. The clock delay circuit generates an opposite effect (additional controllable delay) that cancels out the unwanted delay from finite propagation effects, thereby preventing stability degradation before it occurs even at high sampling frequencies
Data Source
AI summary
Certain aspects of the present disclosure provide methods and apparatus for implementing sampling rate scaling of an excess loop delay (ELD)-compensated continuous-time delta-sigma modulator (CTDSM) analog-to-digital converter (ADC). One example ADC generally includes a loop filter; a quantizer having an input coupled to an output of the loop filter; one or more digital-to-analog converters (DACs), each having an input coupled to an output of the quantizer, an output coupled to an input of the loop filter, and a data latch comprising a clock input for the DAC coupled to a clock input for the ADC; and a clock delay circuit having an input coupled to the clock input for the ADC and an output coupled to a clock input for the quantizer.