Delta-Sigma Modulator Bit Swapping for Low-Loss Switching Amplifiers
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Solution Overview
Problem
Existing devices with delta-sigma modulators and switching amplifiers face challenges in achieving high signal-to-noise ratios (SNR) at high frequencies due to power loss and signal distortion, particularly in audio signal amplification, where high oversampling ratios lead to inefficiencies and limitations in switching amplifier performance.
Innovation Solution
A device with a delta-sigma modulator and a switching amplifier that incorporates a parallel-to-serial converter and a rotation element to convert multi-bit outputs into one-bit PWM-like signals, reducing pulse edges by swapping binary sequences based on the last bit value of preceding words, thereby minimizing switching frequency and power loss while maintaining high SNR.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high oversampling ratios are used in delta-sigma modulators to achieve high SNR, then signal-to-noise ratio is improved, but power loss and signal distortion increase in switching amplifiers at high frequencies
Solution Approach 1:
The patent applies dynamics by making the switching amplifier operate in a dynamic switching mode rather than linear amplification. The delta-sigma modulator converts the audio signal into a high-frequency pulse train that dynamically switches the amplifier between on and off states, allowing the system to achieve high SNR while minimizing power loss through efficient switching operation.
Solution Approach 2:
The patent changes the parameter of sampling frequency by using high oversampling ratios (OSR > 16) to convert the audio signal into a high-frequency pulse train. This parameter change allows the switching amplifier to operate efficiently at high frequencies, achieving both high SNR and low power loss by moving the operation away from the problematic low-frequency region where switching losses are high.
2Measurement precision
If high oversampling ratios are used in delta-sigma modulators, then signal-to-noise ratio is improved, but switching frequency and power consumption increase
Solution Approach 1:
The patent converts the harmful effect of high switching frequency (which normally increases power consumption) into a benefit by using the high-frequency pulse train to drive the switching amplifier in its most efficient operating region. The high frequency allows the amplifier to spend minimal time in the linear region where power dissipation is high, thus converting the potential harm of high frequency into the benefit of efficient switching operation.
3Measurement precision
If multi-bit quantization is used in the DSM to increase SNR, then signal-to-noise ratio is improved, but device complexity and cost increase due to requiring separate power amp channels
Solution Approach 1:
The patent inverts the conventional approach by using a 1-bit quantizer instead of multi-bit quantization. This inversion simplifies the device architecture to a single power amplifier channel while achieving high SNR through the combination of delta-sigma modulation and high-frequency switching amplification, eliminating the need for complex multi-channel architectures.
4Use of energy by moving object
If low oversampling ratios are used for high-frequency baseband signals, then power consumption is reduced, but signal quality and amplification efficiency degrade
Solution Approach 1:
The patent applies periodic action by using high-frequency periodic switching to modulate the audio signal. The delta-sigma modulator generates a periodic pulse train at high frequency that periodically switches the amplifier, allowing low power consumption through efficient switching while maintaining high signal quality through the periodic nature of the modulation that preserves signal integrity.
Data Source
Figure 1a~1b
Figure 2~3
Figure 4a~4b
AI summary
In the prior art, a delta-signal modulator (DSM) having a multi-bit signal at the output is often used and audio signals are often to be amplified. The prior art therefore has a significantly lower frequency range, a narrower bandwidth and correspondingly lower sampling rates. Relatively high oversampling ratios with a higher DSM order (e.g. over 16) are used in order to guarantee an acceptable signal-to-noise ratio (SNR) of the output signals. In order to design a delta-sigma modulator for a switching amplifier so as to achieve a higher SNR in the multi-MHz range and keep the noise-transfer function (NTF) over the useful frequency range as low and flat as possible, claim 1 according to the invention states that a series connection of a parallel-serial converter (PSC) and a downstream swap element (SHS) for the serial output signal ya2 of the parallel serial converter (PSC) is connected to the multi-bit output of the delta-sigma-modulator (DSM), and that the swap element (SHS) swaps, based on the last bit value 0 or 1 of a preceding word in the resulting output signal ya3, the sequence of the binary zeros and ones of the current word (where present), wherein an input signal fed to the delta-sigma-modulator (DSM), said signal being capable of having a frequency range above 25 kHz, is prepared with low oversampling ratio of preferably 8 and high signal-to-noise ratio and 1-0 or 0-1 transitions are largely eliminated at the word boundaries. The invention lies in the field of delta-sigma modulators and related switching amplifiers for use in PLC (power line communication (PLC)) systems.