DAC Pulse Generator With Slew-Controlled Edges for Jitter Reduction
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Solution Overview
Problem
Digital to analog converters face challenges in minimizing clock jitter and maintaining precise current pulse generation due to statistical variations in clock edges, which can lead to errors in feedback loops of analog to digital converter circuits.
Innovation Solution
A digital to analog converter circuit that utilizes a pulse generator producing voltage pulses with slew rate controlled edges, independent of clock edges, to generate current pulses of predetermined length and shape, minimizing clock jitter through a capacitor/reference current circuit, and employs switchable resistors to adjust current amplitude based on digital values, ensuring accurate feedback.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If clock-defined voltage pulses are used to generate current pulses, then the timing is synchronized with the clock signal, but clock jitter causes statistical variations in clock edges leading to errors in feedback loops
Solution Approach 1:
The voltage pulse generation is segmented into two independent parts: the leading edge is controlled by the clock signal for synchronization, while the trailing edge is controlled by a separate RC circuit for precise duration. This segmentation isolates the clock jitter effect to only the leading edge, preventing it from affecting the overall pulse timing and current generation accuracy.
Solution Approach 2:
An RC circuit is introduced as an intermediary element between the clock signal and the current pulse generation. The RC circuit generates the voltage pulse with a controlled trailing edge that is independent of clock jitter, acting as a mediator that translates the clock-triggered event into a precisely timed voltage pulse without transmitting clock variations to the current generation stage.
2Speed
If voltage pulses with clock-defined edges are used, then timing synchronization is achieved, but the current pulse shape and length vary due to clock edge statistical variations
Solution Approach 1:
The voltage pulse characteristics are segmented into two independent control mechanisms: the leading edge timing is controlled by the clock signal for synchronization, while the trailing edge and pulse duration are controlled by an RC circuit with predetermined time constant. This ensures that pulse shape and length remain consistent regardless of clock edge variations.
Solution Approach 2:
The pulse duration and shape parameters are changed from being clock-dependent to being RC-circuit-dependent. By using an RC circuit with a predetermined time constant, the voltage pulse acquires a consistent exponential decay shape that is independent of clock edge variations, thereby maintaining current pulse shape consistency while preserving timing synchronization.
3Measurement precision
If high bandwidth amplifiers are used to maintain accuracy in current pulse generation, then precision is improved, but device complexity and cost increase
Solution Approach 1:
The invention converts the potential harm of clock jitter into a benefit by using the RC circuit's natural exponential charging and discharging characteristics. The RC circuit transforms the clock-triggered event into a smoothly decaying voltage pulse with predetermined shape, which inherently filters out high-frequency noise and reduces the bandwidth requirements for subsequent amplifiers while maintaining accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively minimizes clock-jitter-induced errors by generating current pulses with controlled edges and shapes, maintaining accuracy and reducing the need for high bandwidth amplifiers, thus enhancing the precision and reliability of digital to analog conversions.
Implementation Method 1
The voltage pulses generated by the pulse generator include an edge that is not clock defined. With some embodiments, the edge is characterized as a slew rate controlled pulse edge whose rate of change is independent of a clock edge. In some embodiments, the slew rate of the edge is defined by a capacitor/reference current circuit of the pulse generator circuit.
Implementation Method 2
The voltage to current converter includes a set of switchable resistors where the resistance value provided by the set is dependent upon a digital value of a digital signal. The current amplitude of the current pulses is dependent upon the resistance value and is indicative of the digital value.
Data Source
AI summary
A digital to analog converter (DAC) circuit includes pulse generator circuit for generating voltage pulses having a predetermined length and shape. The voltage pulses are used to control the generation of current pulses generated by a voltage to current converter. The voltage to current converter includes a set of switchable resistors where the resistance value provided by the set is dependent upon a digital value of a digital signal. In some embodiments, the current amplitude of the current pulses is dependent upon the resistance value and is indicative of the digital value.