Delta-Sigma ADC Pre-Charging for High-Impedance Inputs

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Solution Overview

Problem

Existing ADC devices with delta-sigma topology face challenges in handling high source impedance inputs, as they require buffers to prepare signals for sampling, leading to increased cost, layout size, and power consumption, and removing these buffers is not a viable solution.

Innovation Solution

The implementation of a delta-sigma ADC topology that includes a pre-charge capacitor bank and a pre-charge signal generator, where the pre-charge signal is generated based on the quantizer output code and applied during the sampling phase to reduce the average current drawn from the input signal node, thereby increasing the input impedance without the need for additional buffers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If buffers are added to prepare input signals for sampling, then the ADC can handle high source impedance inputs, but the cost, layout size, and power consumption increase

Engineering Contradiction:

Improvecompatibility with high source impedance inputsVSAvoidlayout size

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent combines the buffer functionality with the existing sampling capacitor bank and integrator circuitry. The sampling capacitor bank is configured to perform both sampling and buffering functions, eliminating the need for separate buffer components. This merging approach maintains compatibility with high source impedance inputs while reducing layout size and device complexity.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The sampling capacitor bank is designed to serve multiple functions: it acts as both the sampling element and the buffer for high impedance inputs. The integrator circuit also performs dual roles in signal integration and impedance matching. This multi-functionality approach allows the ADC to handle high source impedance inputs without adding dedicated buffer components, thereby reducing layout size.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If buffers are added to prepare input signals for sampling, then the ADC can handle high source impedance inputs, but power consumption increases

Engineering Contradiction:

Improvecompatibility with high source impedance inputsVSAvoidpower consumption

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The patent merges the buffer function with the sampling capacitor bank and integrator, eliminating the need for separate buffer amplifiers that would consume additional power. The sampling capacitor bank is configured to directly interface with high source impedance inputs, and the integrator performs the signal conditioning without requiring extra power-hungry buffer stages.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The sampling capacitor bank and integrator circuitry are designed to self-condition the input signal from high impedance sources without requiring external buffer assistance. The circuit inherently performs the impedance matching and signal preparation functions through its natural operation, reducing overall power consumption by eliminating dedicated buffer components.

Inventive Principle:

Principle #25Self-service

3Adaptability or versatility

If buffers are added to prepare input signals for sampling, then the ADC can handle high source impedance inputs, but the ADC noise increases

Engineering Contradiction:

Improvecompatibility with high source impedance inputsVSAvoidADC noise

Core Design Contradiction:

Adaptability or versatilityVSObject-generated harmful factors

Solution Approach 1:

The patent combines the buffer function with the sampling capacitor bank and integrator, eliminating separate buffer amplifier stages that would introduce additional noise. By using the existing low-noise sampling and integration circuitry to handle high impedance inputs, the overall noise floor is kept lower than it would be with additional buffer amplifiers.

Inventive Principle:

Principle #5Merging (Combining)

4Device complexity

If buffers are removed from the ADC topology, then cost and layout size decrease, but the ADC cannot handle high source impedance inputs

Engineering Contradiction:

Improvelayout sizeVSAvoidcompatibility with high source impedance inputs

Core Design Contradiction:

Device complexityVSAdaptability or versatility

Solution Approach 1:

The sampling capacitor bank is pre-configured during the sampling phase to capture and hold the input signal from high impedance sources. The integrator is pre-biased and ready to immediately integrate the sampled signal. This preliminary preparation allows the circuit to directly interface with high source impedance inputs without requiring additional buffer stages, maintaining both simplicity and compatibility.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS10284222B1Delta-sigma converter with pre-charging based on quantizer output code

Publication Date: 2019.05.07 TEXAS INSTRUMENTS INC

AI summary

An analog-to-digital converter (ADC) device includes a delta-sigma modulator having at least one integrator and a quantizer configured to receive an output of the at least one integrator. The delta-sigma modulator also includes digital-to-analog converter (DAC) capacitor bank, a sampling capacitor bank, and a pre-charge capacitor bank, each selectively coupled to an input node of the at least one integrator. The delta-sigma modulator also includes a pre-charge signal generator coupled to the pre-charge capacitor bank. The pre-charge signal generator is configured to generate a pre-charge signal to charge the pre-charge capacitor bank based at least in part on an output code of the quantizer.