Shared Amplifier Delta-Sigma ADC for Lower Power and Higher SNR
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Solution Overview
Problem
Conventional delta-sigma analog-to-digital converters (ADCs) face challenges in reducing power consumption while maintaining a high signal-to-noise ratio (SNR), as they require high power amplifiers during the integrating phase and consume excessive power due to multiple ADC copies in multiple channel systems.
Innovation Solution
A dual delta-sigma ADC system with a shared operational amplifier, where one modulator integrates while the other holds its output value using a low power amplifier, reducing overall power consumption while maintaining SNR by interleaving and decimating signals to generate a high resolution digital output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple ADC copies are used in multiple channel systems, then channel capacity is improved, but power consumption increases excessively
Solution Approach 1:
The patent merges multiple ADC channels into a single integrated converter that processes multiple channels sequentially. The shared converter is time-multiplexed across different channels, combining the functionality of multiple independent ADCs into one unit, thereby reducing power consumption while maintaining multi-channel capacity.
Solution Approach 2:
The patent implements periodic switching between different ADC channels using a single converter. The converter alternates between channels in a time-multiplexed manner, with each channel being processed during specific time intervals. This periodic action allows one converter to serve multiple channels without requiring parallel converters for each channel.
2Measurement precision
If high power amplifiers are used during integrating phase, then signal-to-noise ratio is improved, but overall power consumption increases
Solution Approach 1:
The patent uses periodic switching between integrating and holding phases. During integrating phase, the high-power amplifier operates to achieve accurate signal conversion and maintain SNR. During holding phase, the amplifier is switched off or operated at low power, significantly reducing overall power consumption while maintaining measurement precision through the holding capacitor that preserves the integrated value.
Solution Approach 2:
The patent dynamically switches the operational state of the amplifier between high-power integrating mode and low-power holding mode. The system adapts its power consumption level based on the operational phase, using high power only when necessary for accurate integration and low power when maintaining the signal value, thereby optimizing the trade-off between SNR and power consumption.
3Speed
If multiple ADC copies operate in parallel, then processing speed is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple ADC channel processing functions into a single converter unit with time-multiplexed operation. Instead of having separate parallel ADC copies, one integrated converter handles multiple channels sequentially through controlled switching, reducing device complexity while maintaining processing capability through efficient time management.
Data Source
AI summary
A dual delta-sigma modulator includes a first modulator, a second modulator, and a shared amplifier coupled to the first and second modulators. The first modulator includes an integrator configured to generate a first modulator output signal. The second modulator includes a second integrator configured to generate a second modulator output signal. The shared amplifier is configured to assist the first integrator integrating a difference between a first analog input signal and a first modulator output signal from the first modulator during a first period of time and to assist the second integrator integrate a difference between a second analog input signal and a second modulator output signal from the second modulator during a second period of time.