Auto-routing Jog Eliminator for IC Wire Integrity
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Solution Overview
Problem
Current integrated circuit wiring layout systems create unnecessary jogs during the masking process due to minimum feature distance requirements, leading to extra edges and corners that decrease design yield and require costly manual corrections.
Innovation Solution
A wire routing method that determines and assigns costs to various placements of wires relative to shapes to minimize jog creation, selecting the placement with the lowest cost to avoid undesirable jogs, integrated into an auto router system to eliminate or reduce small jogs during the masking process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the auto router places wires according to minimum feature distance rules, then wire integrity is maintained, but undesirable jogs are created during masking
Solution Approach 1:
The system performs preliminary analysis of wire placements before final routing, identifying positions that will cause jogs during masking. By predicting jog creation in advance and selecting alternative placements, the system prevents harmful jogs while maintaining minimum feature distance requirements.
Solution Approach 2:
The system evaluates multiple placement parameters (horizontal and vertical offsets) for each wire connection. By changing placement parameters to select positions with lower jog risk, the system maintains manufacturing precision while reducing undesirable jog creation.
2Object-generated harmful factors
If manual wire straightening programs are used after routing, then jog creation is reduced, but development cost increases
Solution Approach 1:
The auto router system performs self-correction by integrating jog prediction and placement optimization directly into the routing algorithm. The system automatically selects placements that minimize jogs without requiring external post-processing programs, eliminating additional development costs while reducing jog creation.
Solution Approach 2:
The system merges the jog prediction function with the wire routing function into a single integrated process. By combining these functions, the system achieves jog reduction during the initial routing phase rather than requiring separate post-processing steps, thereby reducing development cost.
3Object-generated harmful factors
If more possible wire placements are evaluated, then jog minimization improves, but computational complexity increases
Solution Approach 1:
The system segments the evaluation of wire placements by considering horizontal and vertical offsets separately and systematically. By dividing the placement space into discrete segments based on minimum feature distance requirements, the system evaluates only relevant positions rather than all possible positions, reducing computational complexity while maintaining jog minimization effectiveness.
Data Source
AI summary
In a method of routing a wire to a shape in an integrated circuit for minimizing undesirable jog creation during a masking process, a plurality of possible placements of the wire relative to a selected edge of the shape resulting in the wire being connected to the shape are determined. A cost is assigned to each placement, the cost indicating an amount of jog that would be created in the masking process corresponding to the placement, wherein a greater cost indicates that a greater jog would be created in the masking process than would be created by a placement assigned a lesser cost. A placement having a lowest cost of the plurality of possible placements is selected.