Automatic Rate Sensing for CPRI/OBSAI Serial Clock Detection
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Solution Overview
Problem
Existing CPRI/OBSAI systems face challenges in efficiently detecting the reference clock frequency that matches the data rate, due to the power and area-intensive high-speed circuitry required for Automatic Rate Sense (ARS) detection.
Innovation Solution
A method and apparatus that utilize a phase locked loop (PLL) and an Automatic Rate Sense (ARS) state machine to determine the matching clock frequency by starting a timeout counter, enabling PLL, checking channel synchronization, and repeating the process for each clock frequency from highest to lowest, with comma detection and code-group synchronization, to efficiently match the detected data rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high speed circuitry is used for ARS detection, then detection accuracy is improved, but power consumption and area increase
Solution Approach 1:
The patent replaces high-speed circuitry with a state machine-based software algorithm that runs on a processor. The ARS detection is performed through sequential operations including timeout counter management, PLL enabling, channel synchronization checking, and data rate comparison, rather than using dedicated high-speed hardware circuits. This substitution significantly reduces power consumption and area while maintaining detection accuracy.
Solution Approach 2:
The patent changes the operational parameters by using a timeout counter to manage the detection process and by sequentially testing clock frequencies from highest to lowest. The state machine controls the detection flow through defined states, changing the approach from continuous high-speed circuit operation to discrete, managed parameter changes that reduce power consumption.
2Measurement precision
If high speed circuitry is used for ARS detection, then detection accuracy is improved, but chip area increases
Solution Approach 1:
The patent replaces high-speed circuitry with a state machine-based software algorithm that runs on a processor. The ARS detection is performed through sequential operations including timeout counter management, PLL enabling, channel synchronization checking, and data rate comparison, rather than using dedicated high-speed hardware circuits. This substitution significantly reduces power consumption and area while maintaining detection accuracy.
Solution Approach 2:
The patent uses a universal processor-based state machine to perform multiple functions including timeout management, PLL control, channel synchronization detection, and data rate comparison. This multi-functional approach eliminates the need for dedicated ARS detection circuits, reducing chip area while maintaining detection capabilities.
3Use of energy by moving object
If sequential clock frequency testing is used, then power consumption is reduced, but detection time increases
Solution Approach 1:
The patent performs preliminary actions by first managing the timeout counter and enabling the PLL before actually beginning the clock frequency testing sequence. The state machine is prepared in advance with the correct sequence of operations, and the timeout counter is initialized to define the maximum detection time. This preliminary preparation ensures efficient execution of the sequential testing and reduces overall detection time despite the iterative approach.
Solution Approach 2:
The patent implements feedback mechanisms through the timeout counter that monitors detection progress and through the state machine that receives feedback about channel synchronization status. When channel synchronization is achieved or the timeout expires, the state machine adjusts its behavior accordingly, providing feedback-driven control that optimizes detection time while maintaining low power consumption during the sequential testing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables robust and efficient detection of the correct clock frequency, facilitating ARS lock and improving the detection of high-speed serial signals in low-speed digital domains, even in challenging bit error environments.
Implementation Method 1
enabling a phase locked loop (PLL) following the step of starting the timeout counter
Data Source
AI summary
As part of the protocol for Common Public Radio Interface/Open Base Station Architecture Initiative (CPRI/OBSAI) systems, multiple data rates are support, which are each supported by one or more reference clock frequencies. Traditionally, timing circuits present used for the physical layer (PHY) paths to determine the data rates for the serial data have been plagued with numerous problems. Here, however, a circuit that performs an automatic rate sense (ARS) of high speed serial signals in a low speed digital domain is provided, which is also relatively easy to implement and robust.