Receiver Initialisation TRIZ Cases

A fast-locking unit adjusts sampling clock phase to cut relocking delay when burst-mode data resumes after stall mode.

An FLL-PLL loop recovers clock frequency and phase from incoming data, enabling accurate reference-less CDR in space- and power-limited modules.

Staged calibration aligns main and adaptive DFE sampling clocks during live traffic to correct phase drift without interrupting data output.

Multiple reference clocks and staged logic detect data frequency for accurate phase lock with lower power use and less circuit complexity.

An on-chip oscillator sweeps sampling frequency in a SERDES receiver to avoid external PLL clocks, cutting power and chip area.

An on-chip oscillator sweeps sampling frequency in a SERDES receiver to remove external PLLs, cutting power use and chip area.

Per-bit clock recovery aligns strobe and data sampling clocks to cut skew, noise, and encoding overhead in high-speed parallel I/O.

A hybrid CMOS-bipolar retiming circuit cuts power and voltage overhead by using half-rate clocking for high-speed data paths.

Calibrated delay elements and early-late phase detection reduce PI nonlinearity, improving CDR timing accuracy and lowering BER.

A single-loop referenceless CDR uses strobe-point detection to widen pull-in range, improve jitter tolerance, and cut power.

Detects saddle-point locking in clock and data recovery loops, then triggers fast-phase correction to cut lock time under noise.

Multiple reference clocks detect data frequency and guide phase lock, cutting CDR circuit power use and logic complexity.

Variable delay calibration corrects data-strobe phase errors in high-speed links, preserving signaling margin across voltage and temperature changes.

Phase-difference timing estimation lets one receiver circuit handle acquisition and tracking across modulation schemes with lower power and complexity.

An on-chip oscillator and frequency sweep let a SERDES receiver lock sampling frequency without external clocks or PLLs, cutting power and area.

A small-gain drift correction loop updates CDR oscillation frequency during phase lock, avoiding re-locking and preserving data reception efficiency.

Using only two samples per UI, this CDR uses coarse and fine phase steps to cut lock time while keeping power low.

Interrupt-based PWM phase feedback replaces slow PLL locking, synchronizing clocks within two sync periods while adapting to changing states.

Overlapping digital frequency measurements keep clock ratios current during drift or ramping, reducing synchronizer latency and interruptions.

Frequency and phase detection let a connecting interface recover a stable clock without a crystal oscillator, cutting cost and temperature drift.

Shared PLL and signal channels let one receiver switch across HDMI, MHL, and DP modes, cutting redundant hardware and circuit complexity.

Programmable CDR settings enable on-the-fly clock recovery across wide data rates and protocols without power-down or channel interruption.

A burst-mode and PLL handoff shortens clock recovery lock time while suppressing jitter and tracking errors in high-speed reception circuits.

Dual gated VCOs and frequency detectors let this half-rate CDR improve jitter tolerance without degrading jitter transfer.

Phase detection and delayed logic let a burst-mode CDR switch modes during dead times to prevent clock drift and missed data.

Mislock counting adjusts the CDR loop integral register to acquire reference clocks under large frequency offsets without eye scope latch hardware.

End nodes detect nearby base stations and update access-node neighbor data, reducing manual setup and air-link routing overhead.

Partial Reed-Solomon transmission stops after decode acknowledgment, improving RPMA erasure handling and link reliability.

Adaptive edge-clock resynchronization maintains approximate quadrature in CDR circuits, improving sampling margins under data stream drift.

Forward error correction sends encoded data in parts and stops on decode acknowledgment, improving RPMA reliability while cutting time and energy.

Adaptive Reed-Solomon transmission stops after successful decoding feedback, improving RPMA data reliability while limiting time and energy use.

Periodic reset of accumulated phase data improves lock detection accuracy in clock recovery by limiting drift and wraparound errors.

Phase interpolation aligns recovered clocks across demultiplexed DQPSK streams, reducing phase uncertainty and bit ordering errors.

Variable delay and oversampling correct data-strobe phase errors in high-speed links, preserving sampling margin under voltage and temperature shifts.

A CDR hold scheme stores frequency ratios and switches detectors to keep clock lock through signal loss, interruptions, and unknown input rates.

Oversampling plus cosine and sine transforms lets a CDR circuit detect phase lock without a PLL, known bit pattern, or reference clock.

A PLL and ARS state machine detect the correct CPRI/OBSAI serial clock in a low-speed digital domain, cutting high-speed circuit power and area.

Counts synthesized pulses during frequency comparison to detect PLL lock and switch non-synchronous receivers from frequency to phase acquisition.

A staged GVCO-based clock recovery circuit separates frequency and phase locking to cut bit errors and meet fast lock-time needs.

Embedded clock codes let the source driver recover timing from display data, removing clock-line skew and enabling faster intra-panel transmission.

An edge-triggered reset and prelocked oscillator cut burst-mode start-up delay while maintaining phase lock and jitter tolerance.

A data-detected switch between phase and frequency detectors keeps burst-mode GPON CDR clocks aligned and prevents drift during dead time.

Split FEC packets across routes and stop redundant transmission after successful decoding to improve RPMA reliability without extra airtime.

Periodic timing signals align RPMA access points and spreading codes, improving quasi-orthogonality, SNR, and robust data transmission.

Dynamic CDR gain adjustment and reset shorten sync acquisition time, preventing link failures caused by lost synchronization.

Sigma-delta fine control in a VCO-based CDR cuts integral-word quantization noise and improves jitter tolerance without added area or power.

One configurable SerDes adapts lock timing and jitter behavior for point-to-point and PON links, cutting design and manufacturing complexity.

Periodic reference-clock calibration keeps a low-power oscillator accurate while cutting continuous power draw and EMI noise.

A shared strobe line carries the DBI signal to cut bus transitions, improve signal integrity, and avoid dedicated DBI pins.

Dual phase control loops combine edge and data sampling to improve high-speed clock recovery accuracy and reduce bit errors.