CDR Circuit Drift Correction During Phase Lock
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Solution Overview
Problem
In clock data recovery (CDR) circuits, long-term continuous data reception can lead to frequency fluctuations due to temperature changes or power supply voltage fluctuations, causing the oscillation frequency to drift and resulting in desynchronization of the clock signal with received data, necessitating frequent re-locking operations that reduce data transmission efficiency.
Innovation Solution
A CDR circuit with a frequency-locked loop and phase-locked loop, along with a drift correction circuit that adjusts the oscillation frequency using a smaller loop gain than the frequency-locked loop, allowing for phase lock synchronization without resuming the frequency lock operation, even in the presence of frequency fluctuations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If frequency lock operation is performed using reference clock, then frequency synchronization is achieved, but phase lock cannot be maintained during long-term continuous reception due to frequency drift
Solution Approach 1:
The patent performs frequency lock operation in advance using a reference clock before phase lock operation. This preliminary frequency synchronization ensures that when phase lock operation begins, the frequency is already stabilized, allowing phase lock to be maintained throughout long-term continuous reception without interruption.
Solution Approach 2:
The patent enables continuous phase lock operation for long periods by establishing frequency lock beforehand. The phase locked loop continuously adjusts phase while the frequency remains stable, maintaining uninterrupted data reception and processing throughout extended operation periods.
2Reliability
If re-locking operation is performed frequently to correct frequency drift, then synchronization is maintained, but data transmission efficiency decreases
Solution Approach 1:
The patent performs frequency lock operation in advance using a reference clock before phase lock operation. This preliminary frequency synchronization ensures that when phase lock operation begins, the frequency is already stabilized, allowing phase lock to be maintained throughout long-term continuous reception without interruption.
Solution Approach 2:
The patent enables continuous phase lock operation for long periods by establishing frequency lock beforehand. The phase locked loop continuously adjusts phase while the frequency remains stable, maintaining uninterrupted data reception and processing throughout extended operation periods.
3Speed
If oscillation frequency is corrected using large loop gain, then frequency drift is corrected quickly, but phase lock stability is compromised
Solution Approach 1:
The patent performs frequency lock operation in advance using a reference clock before phase lock operation. This preliminary frequency synchronization ensures that when phase lock operation begins, the frequency is already stabilized, allowing phase lock to be maintained throughout long-term continuous reception without interruption.
Solution Approach 2:
The patent enables continuous phase lock operation for long periods by establishing frequency lock beforehand. The phase locked loop continuously adjusts phase while the frequency remains stable, maintaining uninterrupted data reception and processing throughout extended operation periods.
Data Source
AI summary
A clock data recovery (CDR) circuit is provided with a circuit that updates a locked oscillation frequency, with a small loop gain, after phase lock based on a phase-locked loop circuit for a frequency-locked frequency is completed by a frequency-locked loop circuit or during a phase lock operation. Since the locked oscillation frequency is updated with a small loop gain, it is possible to correct a fluctuation in a frequency of an oscillation circuit in the frequency-locked loop circuit without oscillating a phase-locked loop undesirably even during a phase lock operation.