Reconfigurable CDR Architecture for Wide-Range Multi-Protocol Clock Recovery
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Solution Overview
Problem
Current clock data recovery (CDR) signaling technologies face challenges in supporting a wide range of communications standards and protocols, requiring a high-performance, low-power architecture that is dynamically reconfigurable without disrupting other device components, and often struggle with phase skew issues due to embedded clock signals.
Innovation Solution
The development of programmable CDR circuitry that uses a reference clock signal with programmable dividers, charge pump, loop-filter, and voltage-controlled oscillator (VCO) blocks to recover embedded clock signals, allowing dynamic reconfiguration to support various standards and protocols on-the-fly, eliminating the need for power down and minimizing phase skew.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If CDR circuitry is designed to support multiple communications standards and protocols, then adaptability is improved, but device complexity increases
Solution Approach 1:
The CDR circuitry employs dynamic reconfiguration capabilities where programmable dividers, charge pump currents, loop-filter parameters, and VCO frequencies can be adjusted in real-time to adapt to different communications standards and protocols without requiring multiple dedicated circuits for each standard
Solution Approach 2:
A single CDR circuitry design serves multiple functions by supporting various communications standards (GIGE, XAUI, PIPE, SONET, PCI-E) and protocols through programmable parameters, eliminating the need for separate dedicated CDR circuits for each standard
2Adaptability or versatility
If CDR circuitry is reconfigured to support different standards, then adaptability is improved, but reconfiguration time increases
Solution Approach 1:
The circuitry pre-loads multiple sets of operational parameters (divider ratios, charge pump currents, loop-filter settings, VCO frequencies) into memory or configuration registers, allowing rapid switching between standards by simply changing the active parameter set without time-consuming physical reconfiguration
Solution Approach 2:
The CDR circuitry enables on-the-fly reconfiguration during operation, allowing standards changes without powering down the device or interrupting other channels, minimizing system downtime and maintaining continuous operation
3Speed
If reference clock frequency is increased to support higher data rates, then speed is improved, but power consumption increases
Solution Approach 1:
The reference clock signal path is divided into multiple stages with programmable dividers that can selectively divide the reference clock frequency before it reaches the VCO and CDR circuitry, allowing the system to operate at lower effective frequencies for lower data rates and thus reducing power consumption
Solution Approach 2:
The system dynamically adjusts operational parameters including divider ratios, charge pump currents, loop-filter bandwidth, and VCO frequencies based on the required data rate, optimizing power consumption by using minimal necessary frequencies and currents for each operating condition
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables operation across a wide range of data rates and protocols, supports multi-crystal and independent channel operations, and allows reprogramming of one channel while others remain operational, reducing power consumption and eliminating the need for power down during reconfiguration.
Implementation Method 1
voltage-controlled oscillator (VCO) blocks to recover embedded clock signals
Implementation Method 2
Phase locked loop which includes a voltage controlled oscillator (VCO)
Implementation Method 3
charge pump, loop-filter, and voltage-controlled oscillator (VCO) blocks
Data Source
AI summary
Wide range and dynamically reprogrammable CDR architecture recovers an embedded clock signal from serial input data with a wide range of operating frequencies. In order to support a wide range of data rates, the CDR architecture includes multiple operating parameters. These parameters include various pre/post divider settings, charge pump currents, loop-filter and bandwidth selections, and VCO gears. The parameters may be dynamically reprogrammed without powering down the circuitry or PLD. This allows the CDR circuitry to switch between various standards and protocols on-the-fly.