CDR Phase Lock Indicator Using Oversampling and Transform Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for generating a clock data recovery phase locked indicator are inadequate for clock data recovery circuits not based on phase-locked loops, as they require a known bit pattern and reference clock, limiting their effectiveness.
Innovation Solution
A circuit and method utilizing an oversampling logic unit, alternating current estimator, and logic processor to generate a clock data recovery phase locked indicator through discrete cosine and sine transforms on alternating current terms, eliminating the need for a phase-locked loop locked indicator, known bit pattern, and known reference clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If known bit pattern and reference clock are used to generate CDR phase locked indicator, then the indicator can be generated for phase-locked loop based circuits, but the method cannot be applied to non phase-locked loop based clock data recovery circuits
Solution Approach 1:
The system uses itself to generate the phase locked indicator by processing its own output data through oversampling and correlation operations, eliminating the need for external reference clock or known bit patterns. The CDR circuit's own output is correlated with the input data to determine lock status
Solution Approach 2:
The essential feature for generating the phase locked indicator is extracted from the data stream itself through oversampling and correlation operations, separating the indicator generation function from the traditional reference-based methods. This allows the indicator to be generated from the data content rather than external references
2Adaptability or versatility
If oversampling and transform operations are performed on data to generate phase locked indicator, then the method becomes applicable to non phase-locked loop circuits, but the computational complexity increases
Solution Approach 1:
The data processing is divided into distinct stages: oversampling operation to generate multiple samples, correlation operation to compare samples with input data, and threshold comparison to determine lock status. This segmentation allows each operation to be optimized and implemented efficiently in digital logic
Solution Approach 2:
The system changes the sampling rate parameter by performing oversampling at multiple times the data rate, then processes the sampled data through correlation with specific timing relationships. This parameter transformation converts the complex synchronization problem into a series of simpler digital comparisons
Data Source
AI summary
A circuit includes an oversampling logic unit, an alternating current estimator, and a logic processor. The oversampling logic unit generates a plurality of alternating current terms according to an oversampling clock, and outputs a plurality of alternating current terms corresponding to an output clock from the plurality of alternating current terms according to the output clock. The alternating current estimator executes a discrete cosine transform and a discrete sine transform on a plurality of alternating current terms outputted from the oversampling logic unit within a first predetermined time to generate a first value and a second value respectively. The logic processor compares a number of first values and a number of second values within a second predetermined time, and generates a clock data recovery phase locked indicator according to a comparing result.