PI-Based CDR Calibration for Phase Interpolator Nonlinearity
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Solution Overview
Problem
Phase Interpolator (PI)-based Clock and Data Recovery (CDR) circuits face challenges with non-linearity errors due to process variations and routing mismatches, leading to inaccurate clock timing and increased bit-error-rate (BER) in high-speed serial communication systems.
Innovation Solution
A method for managing estimation and calibration of non-ideality in PI-based CDR circuits using a Digital Delay Control Code (DDCC) and Binary Control Code (BCC) to calibrate programmable delay elements and multiplexers, employing early-late detection for precise phase alignment and error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a PLL-based CDR is used for each data signal, then clock timing accuracy is improved, but power consumption and silicon area increase significantly
Solution Approach 1:
The patent combines multiple CDR functions into a single shared PLL infrastructure. Instead of having separate PLLs for each data signal, one PLL generates a common clock that is distributed to multiple data paths, significantly reducing power consumption and silicon area while maintaining timing accuracy through individual phase interpolation for each data signal
2Measurement precision
If a PLL-based CDR is used for each data signal, then clock timing accuracy is improved, but silicon area increases significantly
Solution Approach 1:
The patent merges multiple CDR operations into a single PLL core that serves all data signals. The shared PLL infrastructure eliminates the need for multiple large filter capacitors and high-speed components, reducing silicon area by approximately 75% compared to dedicated PLL-based CDR for each data signal
3Ease of manufacture
If process variations and routing mismatches are present, then manufacturing cost is reduced, but non-linearity errors increase
Solution Approach 1:
The patent implements a feedback-based calibration mechanism that measures the actual phase output of the PI and compares it against the ideal phase code. The system automatically adjusts calibration parameters to compensate for non-linearity errors caused by process variations and routing mismatches, achieving manufacturing precision without increasing manufacturing complexity
Solution Approach 2:
The patent changes the operational parameters of the PI by applying calibration codes that adjust the phase interpolation characteristics. By dynamically modifying the phase code mapping and delay element settings, the system compensates for manufacturing variations and reduces non-linearity errors without requiring tighter manufacturing tolerances
4Manufacturing precision
If PI calibration is performed for all phase codes, then manufacturing precision is improved, but time required for calibration increases
Solution Approach 1:
The patent applies partial calibration by focusing calibration efforts on critical phase codes that have the greatest impact on overall system performance. Instead of uniformly calibrating all phase codes, the system identifies and calibrates only the most significant phases, reducing calibration time while maintaining adequate phase linearity across the full range
Data Source
AI summary
A system and method for managing estimation and calibration of non-ideality of a Clock and Data Recovery circuit includes phase interpolators (PIs), first and second sets of delay elements, and a clock delay element. A first delay element of the first set of delay elements is programmed using a first digital delay control code (DDCC). The clock delay element is calibrated using a digital external delay control code (DEDCC) till a predetermined criterion is met, and is retained for subsequent use. The remaining delay elements of the first set of delay elements are separately calibrated based on the DEDCC. A first delay element of the second set of delay elements is programmed using a second DDCC. The DEDCC is readjusted for the second set of delay elements. The remaining delay elements of the second set of delay elements are separately calibrated based on the readjusted DEDCC.