Clock Data Recovery Phase Lock Using Multi-Clock Frequency Sampling

Solution Overview

Problem

Existing clock and data recovery circuits face challenges in reducing system power consumption and circuit complexity while achieving accurate phase lock, often requiring high-complexity circuitry and increased power usage for accurate frequency sampling.

Innovation Solution

A clock and data recovery circuit module with a data frequency detection circuit and clock control circuit, utilizing a sampling circuit module, logic circuit modules, and a frequency adjustment circuit to sample data signals with multiple reference clocks, perform logic operations, and adjust frequencies for phase lock, thereby reducing power consumption and complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the receiver detects frequency of the data signal and samples reference clock according to the detected frequency, then phase lock accuracy is improved, but system power consumption increases and circuit complexity increases

Engineering Contradiction:

Improvephase lock accuracyVSAvoidsystem power consumption

Core Design Contradiction:

Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The frequency detection process is segmented into multiple discrete frequency points. Instead of continuously detecting and processing the entire frequency spectrum, the circuit samples at specific predetermined frequency points (e.g., -200ppm, -100ppm, 0ppm, +100ppm, +200ppm). This segmentation reduces the computational burden and power consumption while maintaining adequate phase lock accuracy for practical applications.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The invention uses partial action by sampling only at critical frequency points rather than continuously across the entire frequency range. The oversampling at multiple reference clock frequencies (including frequencies beyond the expected data signal frequency) ensures that the actual frequency is captured among the sampled points, providing sufficient accuracy without the need for exhaustive frequency scanning.

Inventive Principle:

Principle #16Partial or excessive action

2Measurement precision

If the receiver detects frequency of the data signal and samples reference clock according to the detected frequency, then phase lock accuracy is improved, but device complexity increases

Engineering Contradiction:

Improvephase lock accuracyVSAvoidcircuit complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The frequency detection process is segmented into multiple discrete frequency points. Instead of continuously detecting and processing the entire frequency spectrum, the circuit samples at specific predetermined frequency points (e.g., -200ppm, -100ppm, 0ppm, +100ppm, +200ppm). This segmentation reduces the computational burden and power consumption while maintaining adequate phase lock accuracy for practical applications.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The invention uses partial action by sampling only at critical frequency points rather than continuously across the entire frequency range. The oversampling at multiple reference clock frequencies (including frequencies beyond the expected data signal frequency) ensures that the actual frequency is captured among the sampled points, providing sufficient accuracy without the need for exhaustive frequency scanning.

Inventive Principle:

Principle #16Partial or excessive action

3Measurement precision

If multiple reference clocks are used for sampling data signal, then frequency detection accuracy is improved, but circuit complexity increases

Engineering Contradiction:

Improvefrequency detection accuracyVSAvoidcircuit complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

Multiple reference clock circuits are designed with identical structures and functions, each capable of sampling the data signal at a specific frequency offset. This modular approach allows the system to achieve wide frequency detection range and high accuracy by simply activating different instances of the same circuit rather than designing complex specialized circuits for each frequency point.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The frequency detection process is segmented into multiple discrete frequency points. Instead of continuously detecting and processing the entire frequency spectrum, the circuit samples at specific predetermined frequency points (e.g., -200ppm, -100ppm, 0ppm, +100ppm, +200ppm). This segmentation reduces the computational burden and power consumption while maintaining adequate phase lock accuracy for practical applications.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS9716506B2Phase lock method

Publication Date: 2017.07.25 PHISON ELECTRONICS

AI summary

A phase lock method is provided. The method includes: sampling a data signal according to a plurality of reference clocks and outputting a sampling result; performing a first logic operation according to the sampling result and outputting a first logic result; delaying the first logic result and outputting the delayed first logic result; performing a second logic operation according to the first logic result and the delayed first logic result and outputting a second logic result; outputting a first frequency adjustment signal according to the second logic result; and performing a phase lock according to the first frequency adjustment signal and a frequency of the data signal.