Two-Sample CDR Circuit for Fast Clock Locking
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Solution Overview
Problem
High-speed serial interface receivers face challenges in clock and data recovery due to asynchronous data and local clock alignment, leading to prolonged lock times in systems like Low Latency Interface (LLI) applications, where fast memory access is critical but power consumption must be low.
Innovation Solution
A bang-bang phase detector-based clock and data recovery (CDR) circuit that uses only two samples per data period, employing variable step sizes and phase adjustments, including course and fine steps, to rapidly lock the clock signal, achieving lock within 50 UI while maintaining low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a PLL or DLL based CDR circuit is used to implement reference loop, then the clock can be recovered and aligned with data eye center, but the lock time becomes relatively long
Solution Approach 1:
The CDR circuit is segmented into two distinct phases: acquisition mode with coarse phase steps for fast locking, and tracking mode with fine phase steps for precision. This segmentation allows the system to rapidly acquire lock initially, then maintain precise alignment, resolving the contradiction between fast lock time and accurate clock alignment.
Solution Approach 2:
The phase step size is made dynamic rather than fixed. The system automatically adjusts the phase step size based on the locking state: using larger coarse steps during acquisition and smaller fine steps during tracking. This dynamic adjustment enables both fast initial locking and precise final alignment, overcoming the limitation of static phase step approaches.
2Loss of time
If more data samples per period are used to improve locking speed, then lock time is reduced, but power consumption increases
Solution Approach 1:
The system maintains continuous operation with only two samples per data period throughout both acquisition and tracking phases. By using variable phase step sizes instead of increasing sample count, the system achieves continuous useful action for clock recovery without the power penalty of additional sampling, thus reducing lock time while maintaining low power consumption.
Solution Approach 2:
The system changes the parameter of phase step size rather than the number of samples. By varying the phase step size (coarse vs. fine steps) based on locking progress, the system achieves faster locking without increasing the fixed two-sample-per-period rate, thereby reducing lock time while keeping power consumption low.
3Device complexity
If fixed phase steps are used in CDR, then the circuit operation is simple, but the lock time is prolonged
Solution Approach 1:
The phase step size transitions from fixed to dynamic. The system automatically selects between coarse and fine phase steps based on the locking state, adding intelligence to the control logic. This dynamic approach significantly reduces lock time while maintaining relatively simple circuit operation through state-based decision making.
Solution Approach 2:
The system implements feedback by monitoring the locking state and using this information to adjust the phase step size. The early-late detector provides feedback about phase alignment status, which controls whether coarse or fine steps are used. This feedback mechanism enables fast locking while keeping the control logic relatively simple through clear state-based rules.
Data Source
AI summary
A clock and data recovery module (CDR) is configured to perform fast locking using only two samples per each unit interval (UI). Two clock phase signals are selected from a plurality of clock phase signals. A sequence of data bits is sampled at a rate of two times per UI responsive to the two clock phase signals in which a first sample of each UI is designated as an edge sample a second sample is designated as a data sample. Each edge sample is voted as early/late as compared to an associated data transition of the sequence of data bits by comparing each edge sample to a next data sample. The sample clocks are locked such that edge samples occur in proximity to data transitions by iteratively adjusting a phase of the two selected clock phase signals by a variable step size in response to the early/late vote.