Referenceless CDR Circuit With Wide Frequency Acquisition
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Solution Overview
Problem
Conventional dual-loop clock-data recovery (CDR) architectures have a limited capture range, making it difficult to achieve robust frequency acquisition and phase locking, especially in the presence of input jitter and phase detector nonidealities.
Innovation Solution
A referenceless CDR architecture with a single loop, utilizing a digital control circuit, a combined phase and strobe point detector circuit, and an LC voltage control oscillator, which allows for both frequency and phase locking without a frequency detector or lock detector, by introducing a strobe point to enhance the pull-in range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional dual-loop CDR architecture is used, then frequency acquisition and phase locking can be achieved, but the capture range is limited and the device complexity increases
Solution Approach 1:
The patent combines frequency detection and phase detection functions into a single phase detector circuit. The phase detector output provides both frequency acquisition information and phase locking information, eliminating the need for separate frequency detector and lock detector circuits. This merging approach maintains the dual-loop functionality while reducing device complexity.
Solution Approach 2:
The phase detector is designed to serve multiple functions: it detects phase errors for fine tuning and simultaneously provides frequency error information for coarse tuning. The single loop architecture performs both frequency acquisition and phase locking tasks that traditionally required separate loops, achieving multi-functionality with reduced complexity.
2Measurement precision
If a linear CDR with Pottbacker frequency detector is used, then phase locking can be achieved, but the capture range is extremely limited
Solution Approach 1:
The patent implements a dynamic capture range expansion mechanism where the VCO tuning range is adaptively adjusted based on the detected frequency error. The system dynamically switches between coarse tuning (large frequency steps) and fine tuning (small frequency steps) modes, allowing the phase-locked loop to acquire lock over a wide frequency range while maintaining precise phase locking accuracy.
Solution Approach 2:
The system changes the VCO control parameters dynamically during operation. When frequency offset is large, the system uses larger frequency steps for rapid acquisition. When approaching lock, it transitions to smaller frequency steps for precise phase locking. This parameter adaptation enables both wide capture range and high phase locking accuracy.
3Productivity
If the VCO frequency is initially higher than the input data bit rate, then frequency acquisition can start, but the frequency must be decreased to achieve locking
Solution Approach 1:
The patent inverts the traditional frequency acquisition approach by starting with the VCO frequency higher than the input data rate and decreasing it to achieve locking, rather than starting lower and increasing. This inversion is enabled by the phase detector's ability to detect and correct frequency errors in both directions, providing a more reliable acquisition path for certain input conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables a full-rate clock signal recovery with a wide acquisition range, improving jitter tolerance and reducing power consumption by eliminating the need for additional circuitry, while maintaining high capture range and phase locking accuracy.
Implementation Method 1
an LC voltage control oscillator (LC VCO) electrically coupled to the PSPD and DCC such that a frequency of the LC VCO decreases when a negative strobe point is detected
Data Source
AI summary
A full-rate referenceless clock-data recovery architecture with neither a frequency detector nor a lock detector that allows both frequency and phase locking in a single loop. According to one embodiment, a referenceless clock data recovery (CDR) circuit, comprises a digital control circuit (DCC), a phase and strobe point detector circuit (PSPD), and an LC voltage control oscillator (LC VCO) electrically coupled to the PSPD and DCC such that a frequency of the LC VCO decreases when a negative strobe point is detected and an initial frequency of the LC VCO is higher than an input data bit rate.