Source Driver CDR Circuit for Skew-Free Embedded Clock Data
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Solution Overview
Problem
Conventional intra-panel interfaces for display devices face challenges in high-speed serial data transmission due to inevitable skew issues, particularly in chip-on-glass technology where separate data and clock signals are transmitted, limiting the speed of data transmission without skew.
Innovation Solution
A clock and data recovery (CDR) circuit is implemented in the source driver, which includes a clock recovery unit and a delay locked loop unit to accurately recover the clock signal from clock-embedded data, eliminating the need for a dedicated clock signal line by detecting clock edges and generating a multi-phase clock signal, thereby enabling high-speed data and clock transmission without skew.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If separate data and clock signals are transmitted through data line and clock signal line, then clock signal can be transmitted, but skew issue occurs and data transmission speed is limited
Solution Approach 1:
The patent merges the clock signal and data signal into a single transmission channel by embedding the clock signal within the data stream. The clock recovery unit extracts the clock signal from the received data stream, eliminating the need for a separate clock signal line and thereby preventing skew issues while enabling high-speed data transmission.
Solution Approach 2:
The data line is given multi-functionality by making it capable of transmitting both data signals and clock signals. The clock embedded data channel serves dual purposes: conveying pixel data from the timing controller to the source driver while simultaneously carrying the clock signal for synchronization, thus eliminating the need for a dedicated clock line.
2Device complexity
If clock signal is embedded in data stream, then dedicated clock signal line is eliminated, but clock signal recovery becomes complex
Solution Approach 1:
The delay locked loop unit employs feedback mechanisms to automatically adjust and lock onto the embedded clock signal. The phase detector compares the phase of the recovered clock signal with a reference, and the delay element adjusts the phase accordingly, creating a self-correcting system that simplifies clock recovery despite the embedded nature of the signal.
Solution Approach 2:
The clock recovery unit acts as an intermediary that extracts and reconstructs the clock signal from the embedded data stream. This intermediary component bridges the gap between the embedded clock signal in the data stream and the clean clock signal needed by the source driver, simplifying the overall recovery process.
3Measurement precision
If multi-phase clock signal is generated, then data sampling accuracy is improved, but circuit complexity increases
Solution Approach 1:
The delay locked loop unit generates multiple phase versions of the clock signal by creating delayed copies of the recovered clock signal. These multi-phase clock signals are segmented versions of the original clock, each offset in phase, allowing for more accurate sampling of incoming data at different time points within the clock cycle.
Solution Approach 2:
The system changes the temporal parameter of the clock signal by generating multiple phase versions with different time offsets. This parameter transformation allows the source driver to sample data at optimal points in the clock cycle, improving sampling accuracy without requiring fundamentally different circuit architecture.
Data Source
AI summary
A clock and data recovery (CDR) circuit of a source driver includes a clock recovery unit and a delay locked loop unit. The clock recovery unit receives data bits and a clock code periodically inserted into the data bits through a clock embedded data channel in a display data mode, and is configured to generate a clock signal by detecting an edge of the clock code. The delay locked loop unit is configured to generate a multi-phase clock signal based on the clock signal in the display data mode.